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[209.85.219.174]) by smtp.gmail.com with ESMTPSA id 00721157ae682-62a0a56e642sm27077897b3.135.2024.05.30.00.12.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 30 May 2024 00:12:18 -0700 (PDT) Received: by mail-yb1-f174.google.com with SMTP id 3f1490d57ef6-dfa49a90146so493106276.1; Thu, 30 May 2024 00:12:18 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCW7c7bDMccFYoG73jvAuG7weDZOJCShw1nBtgjLvzRWbbgZQvyzI8Az185t7VgoM1FlGxgilq2QwJY/7M8lo/3pFpnQgrZ4eOU1BIM2qsmCOYleoac6RPuzVTEeHQllP8oO7nP4bG+9CqMqc0Cw2cgg7MmEhSBbjvS2eskfWSwywnzWb49OtN0pSLOemb7KCW7GUzLGQRPQpfPyrZmmh6i2GT9aoFYd X-Received: by 2002:a25:b11f:0:b0:de6:17e7:ddd1 with SMTP id 3f1490d57ef6-dfa5a60f54dmr1404276276.34.1717053137821; Thu, 30 May 2024 00:12:17 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240524082800.333991-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20240524082800.333991-3-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: From: Geert Uytterhoeven Date: Thu, 30 May 2024 09:12:06 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 2/4] dt-bindings: clock: Add R9A09G057 CPG Clock and Reset Definitions To: "Lad, Prabhakar" Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Magnus Damm , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fabrizio Castro , Lad Prabhakar Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Prabhakar, On Wed, May 29, 2024 at 11:10=E2=80=AFPM Lad, Prabhakar wrote: > On Mon, May 27, 2024 at 10:18=E2=80=AFAM Geert Uytterhoeven > wrote: > > On Fri, May 24, 2024 at 10:29=E2=80=AFAM Prabhakar wrote: > > > From: Lad Prabhakar > > > > > > Define RZ/V2H(P) (R9A09G057) Clock Pulse Generator module clock outpu= ts > > > (CPG_CLK_ON* registers), and reset definitions (CPG_RST_* registers) > > > in Section 4.4.2 and 4.4.3 ("List of Clock/Reset Signals") of the RZ/= V2H(P) > > > Hardware User's Manual (Rev.1.01, Feb. 2024). > > > > > > Signed-off-by: Lad Prabhakar > > > > > --- /dev/null > > > +++ b/include/dt-bindings/clock/r9a09g057-cpg.h > > > @@ -0,0 +1,644 @@ > > > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > + * > > > + * Copyright (C) 2024 Renesas Electronics Corp. > > > + */ > > > +#ifndef __DT_BINDINGS_CLOCK_R9A09G057_CPG_H__ > > > +#define __DT_BINDINGS_CLOCK_R9A09G057_CPG_H__ > > > + > > > +#include > > > + > > > +/* Clock list */ > > > > No distinction between Core and Module clocks? > > > I was in two minds here. Would you prefer clocks with no CGC support > to be listed as core clocks? What's CGC support? (Obviously I need some more reading before I can tackle the rest of this series :-) My comments are due to the bindings saying: '#clock-cells': description: | - For CPG core clocks, the two clock specifier cells must be "CPG_COR= E" and a core clock reference, as defined in , - For module clocks, the two clock specifier cells must be "CPG_MOD" = and a module number, as defined in . const: 2 while the header file does not make it obvious whether a clock needs CPG_CORE or CPG_MOD. Gr{oetje,eeting}s, Geert --=20 Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k= org In personal conversations with technical people, I call myself a hacker. Bu= t when I'm talking to journalists I just say "programmer" or something like t= hat. -- Linus Torvalds