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[209.85.219.170]) by smtp.gmail.com with ESMTPSA id 3f1490d57ef6-dfa48f480b0sm595940276.9.2024.05.30.05.51.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 30 May 2024 05:51:36 -0700 (PDT) Received: by mail-yb1-f170.google.com with SMTP id 3f1490d57ef6-dfa67a3e702so373284276.1; Thu, 30 May 2024 05:51:36 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCVszh8/MLGl0Kfo8H1K/Qgj1+IJrvV64I1AaVLt68ceRqYknX0PqxwIyTUVtt466rFe+Xe9hpss0jy6t2YRBm08ZaPElSHepZn21EKTPZg1EH69fOT8sQI+ZEplleGguA2VAKZVrHrxOwo2rfupfOM7DG3q13zRqF+IFc/7AG6iyXYapmwJWnsvpY6XYMTDFtB/SSNvn/s+JzG/B6IH78KhviY9B28P8A== X-Received: by 2002:a25:dcd0:0:b0:dfa:4ad7:19d0 with SMTP id 3f1490d57ef6-dfa5a5b7a11mr2270407276.2.1717073495538; Thu, 30 May 2024 05:51:35 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240524094603.988-1-paul.barker.ct@bp.renesas.com> <20240524094603.988-3-paul.barker.ct@bp.renesas.com> In-Reply-To: <20240524094603.988-3-paul.barker.ct@bp.renesas.com> From: Geert Uytterhoeven Date: Thu, 30 May 2024 14:51:23 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 2/9] pinctrl: renesas: rzg2l: Refactor pin to OEN bit translation To: Paul Barker Cc: Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, "Lad, Prabhakar" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Paul, On Fri, May 24, 2024 at 11:46=E2=80=AFAM Paul Barker wrote: > We currently support setting OEN (Output ENable) bits only for the > RZ/G3S SoC and so the functions rzg2l_oen_is_supported() and > rzg2l_pin_to_oen_bit() are hardcoded for the RZ/G3S. To prepare for > supporting OEN on SoCs in the RZ/G2L family, we need to make this code > more flexible. > > So, the rzg2l_oen_is_supported() and rzg2l_pin_to_oen_bit() functions > are replaced with a single translation function which is called via a > pin_to_oen_bit function pointer and returns an error code if OEN is not > supported for the given pin. > > Signed-off-by: Paul Barker Thanks for your patch! > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c > @@ -256,6 +256,8 @@ struct rzg2l_pinctrl_data { > const struct rzg2l_hwcfg *hwcfg; > const struct rzg2l_variable_pin_cfg *variable_pin_cfg; > unsigned int n_variable_pin_cfg; > + int (*pin_to_oen_bit)(const struct rzg2l_hwcfg *hwcfg, > + u32 caps, u32 offset, u8 pin); > }; This definitely needs synchronization with Prabhakar, as he introduces a different set of function pointers to distinguish RZ/G2L (G3S) and RZ/V2H. We really like to end up with something that is consistent, and works for all. Gr{oetje,eeting}s, Geert --=20 Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k= org In personal conversations with technical people, I call myself a hacker. Bu= t when I'm talking to journalists I just say "programmer" or something like t= hat. -- Linus Torvalds