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bh=laI44R9CkvkoWL5j55C7oR7usS/DpKOSclK7hV4WnUk=; b=0OOtwVHBs60a+zPox/sQdd+j7R 4bmjQkip08Y8wnmyY0Tv1JWfy6VONeDDGxl9RQuZzxekHgjLXZ/SAZY65R0/D0rdvoNud2G/eOYNA nSOfKWU6wfi0ZPgrrNzM1W8NZku2IaiNbGk4OfSMlDlhRKcUnKPKTAQHOcajzcV8CcGs=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1sCfUb-00GLeo-8d; Thu, 30 May 2024 15:06:53 +0200 Date: Thu, 30 May 2024 15:06:53 +0200 From: Andrew Lunn To: Piergiorgio Beruto Cc: Selvamani Rajagopal , "Parthiban.Veerasooran@microchip.com" , "davem@davemloft.net" , "edumazet@google.com" , "kuba@kernel.org" , "pabeni@redhat.com" , "horms@kernel.org" , "saeedm@nvidia.com" , "anthony.l.nguyen@intel.com" , "netdev@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "corbet@lwn.net" , "linux-doc@vger.kernel.org" , "robh+dt@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "conor+dt@kernel.org" , "devicetree@vger.kernel.org" , "Horatiu.Vultur@microchip.com" , "ruanjinjie@huawei.com" , "Steen.Hegelund@microchip.com" , "vladimir.oltean@nxp.com" , "UNGLinuxDriver@microchip.com" , "Thorsten.Kummermehr@microchip.com" , "Nicolas.Ferre@microchip.com" , "benjamin.bigler@bernformulastudent.ch" , Viliam Vozar , Arndt Schuebel Subject: Re: [PATCH net-next v4 00/12] Add support for OPEN Alliance 10BASE-T1x MACPHY Serial Interface Message-ID: <70cf84d1-99ad-4c30-9811-f796f21e6391@lunn.ch> References: <2d9f523b-99b7-485d-a20a-80d071226ac9@microchip.com> <6ba7e1c8-5f89-4a0e-931f-3c117ccc7558@lunn.ch> <8b9f8c10-e6bf-47df-ad83-eaf2590d8625@microchip.com> <44cd0dc2-4b37-4e2f-be47-85f4c0e9f69c@lunn.ch> <6e4c8336-2783-45dd-b907-6b31cf0dae6c@lunn.ch> <0581b64a-dd7a-43d7-83f7-657ae93cefe5@lunn.ch> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Thu, May 30, 2024 at 09:43:56AM +0000, Piergiorgio Beruto wrote: > Hello Andrew, > > I was reading back into the MACPHY specifications in OPEN Alliance, and it seems like MMS 10 to MMS 15 are actually allowed as vendor specific registers. See page 50. > The specifications further say that vendor specific registers of the PHY that would normally be in MMD30-31 (ie, excluding the PLCA registers and the other OPEN standard registers) would go into MMS10 to MMS15. > > So I'm wondering, why is it bad to have vendor specific registers into MMD10 to MMD15? > I think the framework should allow non-standard stuff to be mapped into these, no? From an architecture perspicuity, PHY vendor specific registers should be in the PHY register address space. MAC vendor specific registers should be in the MAC register address space. It seems like the Microchip device has some PHY vendor specific registers in the MAC address space. That is bad. Both your and Microchip device is a single piece of silicon. But i doubt there is anything in the standard which actually requires this. The PHY could be discrete, on the end of an MDIO bus and an MII bus. That is the typical design for the last 30 years, and what linux is built around. The MAC should not assume anything about the PHY, the PHY should not assume anything about the MAC, because they are interchangeable. The framework does allow you to poke any register anywhere. But i would strongly avoid breaking the layering, it is going to cause you long term maintenance problems, and is ugly. Andrew