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Thu, 30 May 2024 14:23:48 GMT Received: from [10.110.83.142] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 30 May 2024 07:23:47 -0700 Message-ID: <24570028-42cf-43b1-95f2-b6f48233bef9@quicinc.com> Date: Thu, 30 May 2024 07:23:47 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/7] pmdomain: core: Enable s2idle for CPU PM domains on PREEMPT_RT To: Ulf Hansson CC: "Rafael J . Wysocki" , Sudeep Holla , , Lorenzo Pieralisi , Nikunj Kela , Prasad Sodagudi , Maulik Shah , Daniel Lezcano , Krzysztof Kozlowski , , , References: <20240527142557.321610-1-ulf.hansson@linaro.org> <20240527142557.321610-2-ulf.hansson@linaro.org> <52dce8d3-acfa-4f2c-92d0-c25aa59d6526@quicinc.com> Content-Language: en-US From: Nikunj Kela In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 14nRJwPA3lpVc2efCHGWHEWKaKbDqHPu X-Proofpoint-GUID: 14nRJwPA3lpVc2efCHGWHEWKaKbDqHPu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.12.28.16 definitions=2024-05-30_09,2024-05-30_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxlogscore=999 phishscore=0 malwarescore=0 impostorscore=0 bulkscore=0 suspectscore=0 priorityscore=1501 clxscore=1015 spamscore=0 mlxscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405170001 definitions=main-2405300109 On 5/30/2024 1:15 AM, Ulf Hansson wrote: > On Tue, 28 May 2024 at 21:56, Nikunj Kela wrote: >> >> On 5/27/2024 7:25 AM, Ulf Hansson wrote: >>> To allow a genpd provider for a CPU PM domain to enter a domain-idle-state >>> during s2idle on a PREEMPT_RT based configuration, we can't use the regular >>> spinlock, as they are turned into sleepable locks on PREEMPT_RT. >>> >>> To address this problem, let's convert into using the raw spinlock, but >>> only for genpd providers that have the GENPD_FLAG_CPU_DOMAIN bit set. In >>> this way, the lock can still be acquired/released in atomic context, which >>> is needed in the idle-path for PREEMPT_RT. >>> >>> Do note that the genpd power-on/off notifiers may also be fired during >>> s2idle, but these are already prepared for PREEMPT_RT as they are based on >>> the raw notifiers. However, consumers of them may need to adopt accordingly >>> to work properly on PREEMPT_RT. >>> >>> Signed-off-by: Ulf Hansson >>> --- >>> >>> Changes in v2: >>> - None. >>> >>> --- >>> drivers/pmdomain/core.c | 47 ++++++++++++++++++++++++++++++++++++++- >>> include/linux/pm_domain.h | 5 ++++- >>> 2 files changed, 50 insertions(+), 2 deletions(-) >>> >>> diff --git a/drivers/pmdomain/core.c b/drivers/pmdomain/core.c >>> index 623d15b68707..072e6bdb6ee6 100644 >>> --- a/drivers/pmdomain/core.c >>> +++ b/drivers/pmdomain/core.c >>> @@ -117,6 +117,48 @@ static const struct genpd_lock_ops genpd_spin_ops = { >>> .unlock = genpd_unlock_spin, >>> }; >>> >>> +static void genpd_lock_raw_spin(struct generic_pm_domain *genpd) >>> + __acquires(&genpd->raw_slock) >>> +{ >>> + unsigned long flags; >>> + >>> + raw_spin_lock_irqsave(&genpd->raw_slock, flags); >>> + genpd->raw_lock_flags = flags; >>> +} >>> + >>> +static void genpd_lock_nested_raw_spin(struct generic_pm_domain *genpd, >>> + int depth) >>> + __acquires(&genpd->raw_slock) >>> +{ >>> + unsigned long flags; >>> + >>> + raw_spin_lock_irqsave_nested(&genpd->raw_slock, flags, depth); >>> + genpd->raw_lock_flags = flags; >>> +} >>> + >>> +static int genpd_lock_interruptible_raw_spin(struct generic_pm_domain *genpd) >>> + __acquires(&genpd->raw_slock) >>> +{ >>> + unsigned long flags; >>> + >>> + raw_spin_lock_irqsave(&genpd->raw_slock, flags); >>> + genpd->raw_lock_flags = flags; >>> + return 0; >>> +} >>> + >>> +static void genpd_unlock_raw_spin(struct generic_pm_domain *genpd) >>> + __releases(&genpd->raw_slock) >>> +{ >>> + raw_spin_unlock_irqrestore(&genpd->raw_slock, genpd->raw_lock_flags); >>> +} >>> + >>> +static const struct genpd_lock_ops genpd_raw_spin_ops = { >>> + .lock = genpd_lock_raw_spin, >>> + .lock_nested = genpd_lock_nested_raw_spin, >>> + .lock_interruptible = genpd_lock_interruptible_raw_spin, >>> + .unlock = genpd_unlock_raw_spin, >>> +}; >>> + >>> #define genpd_lock(p) p->lock_ops->lock(p) >>> #define genpd_lock_nested(p, d) p->lock_ops->lock_nested(p, d) >>> #define genpd_lock_interruptible(p) p->lock_ops->lock_interruptible(p) >>> @@ -2079,7 +2121,10 @@ static void genpd_free_data(struct generic_pm_domain *genpd) >>> >>> static void genpd_lock_init(struct generic_pm_domain *genpd) >>> { >>> - if (genpd->flags & GENPD_FLAG_IRQ_SAFE) { >>> + if (genpd->flags & GENPD_FLAG_CPU_DOMAIN) { >>> + raw_spin_lock_init(&genpd->raw_slock); >>> + genpd->lock_ops = &genpd_raw_spin_ops; >>> + } else if (genpd->flags & GENPD_FLAG_IRQ_SAFE) { >> Hi Ulf, though you are targeting only CPU domains for now, I wonder if >> FLAG_IRQ_SAFE will be a better choice? The description of the flag says >> it is safe for atomic context which won't be the case for PREEMPT_RT? > You have a point! > > However, we also need to limit the use of raw spinlocks, from > PREEMPT_RT point of view. In other words, just because a genpd > provider is capable of executing its callbacks in atomic context, > doesn't always mean that it should use raw spinlocks too. Got it! Thanks. Maybe in future, if there is a need, a new GENPD FLAG for RT, something like GENPD_FLAG_IRQ_SAFE_RT, can be added to address this. > > [...] > > Kind regards > Uffe