Received-SPF: pass (google.com: domain of linux-kernel+bounces-195521-linux.lists.archive=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) client-ip=139.178.88.99;
Precedence: bulk
MIME-Version: 1.0
References: <20240529215458.937817-1-samuel.holland@sifive.com>
In-Reply-To: <20240529215458.937817-1-samuel.holland@sifive.com>
From: Anup Patel <anup@brainfault.org>
Date: Thu, 30 May 2024 19:58:22 +0530
Message-ID: <CAAhSdy2kO5TYfh6-h4R3UWNidzYpp-CN7zL=JmAKdt1Q23TrwQ@mail.gmail.com>
Subject: Re: [PATCH] irqchip/sifive-plic: Chain to parent IRQ after handlers
 are ready
To: Samuel Holland <samuel.holland@sifive.com>
Cc: Thomas Gleixner <tglx@linutronix.de>, Geert Uytterhoeven <geert@linux-m68k.org>, 
	Albert Ou <aou@eecs.berkeley.edu>, Anup Patel <apatel@ventanamicro.com>, 
	Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, 
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable

On Thu, May 30, 2024 at 3:25=E2=80=AFAM Samuel Holland
<samuel.holland@sifive.com> wrote:
>
> Now that the PLIC uses a platform driver, the driver probed later in the
> boot process, where interrupts from peripherals might already be
> pending. As a result, plic_handle_irq() may be called as early as the
> call to irq_set_chained_handler(). But this call happens before the
> per-context handler is completely set up, so there is a window where
> plic_handle_irq() can see incomplete per-context state and crash. Avoid
> this by delaying the call to irq_set_chained_handler() until all
> handlers from all PLICs are initialized.
>
> Fixes: 8ec99b033147 ("irqchip/sifive-plic: Convert PLIC driver into a pla=
tform driver")
> Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
> Closes: https://lore.kernel.org/r/CAMuHMdVYFFR7K5SbHBLY-JHhb7YpgGMS_hnRWm=
8H0KD-wBo+4A@mail.gmail.com/
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>

LGTM.

Reviewed-by: Anup Patel <anup@brainfault.org>

Thanks for fixing this.

Regards,
Anup

> ---
>
>  drivers/irqchip/irq-sifive-plic.c | 34 +++++++++++++++----------------
>  1 file changed, 17 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifi=
ve-plic.c
> index 8fb183ced1e7..9e22f7e378f5 100644
> --- a/drivers/irqchip/irq-sifive-plic.c
> +++ b/drivers/irqchip/irq-sifive-plic.c
> @@ -85,7 +85,7 @@ struct plic_handler {
>         struct plic_priv        *priv;
>  };
>  static int plic_parent_irq __ro_after_init;
> -static bool plic_cpuhp_setup_done __ro_after_init;
> +static bool plic_global_setup_done __ro_after_init;
>  static DEFINE_PER_CPU(struct plic_handler, plic_handlers);
>
>  static int plic_irq_set_type(struct irq_data *d, unsigned int type);
> @@ -487,10 +487,8 @@ static int plic_probe(struct platform_device *pdev)
>         unsigned long plic_quirks =3D 0;
>         struct plic_handler *handler;
>         u32 nr_irqs, parent_hwirq;
> -       struct irq_domain *domain;
>         struct plic_priv *priv;
>         irq_hw_number_t hwirq;
> -       bool cpuhp_setup;
>
>         if (is_of_node(dev->fwnode)) {
>                 const struct of_device_id *id;
> @@ -549,14 +547,6 @@ static int plic_probe(struct platform_device *pdev)
>                         continue;
>                 }
>
> -               /* Find parent domain and register chained handler */
> -               domain =3D irq_find_matching_fwnode(riscv_get_intc_hwnode=
(), DOMAIN_BUS_ANY);
> -               if (!plic_parent_irq && domain) {
> -                       plic_parent_irq =3D irq_create_mapping(domain, RV=
_IRQ_EXT);
> -                       if (plic_parent_irq)
> -                               irq_set_chained_handler(plic_parent_irq, =
plic_handle_irq);
> -               }
> -
>                 /*
>                  * When running in M-mode we need to ignore the S-mode ha=
ndler.
>                  * Here we assume it always comes later, but that might b=
e a
> @@ -597,25 +587,35 @@ static int plic_probe(struct platform_device *pdev)
>                 goto fail_cleanup_contexts;
>
>         /*
> -        * We can have multiple PLIC instances so setup cpuhp state
> +        * We can have multiple PLIC instances so setup global state
>          * and register syscore operations only once after context
>          * handlers of all online CPUs are initialized.
>          */
> -       if (!plic_cpuhp_setup_done) {
> -               cpuhp_setup =3D true;
> +       if (!plic_global_setup_done) {
> +               struct irq_domain *domain;
> +               bool global_setup =3D true;
> +
>                 for_each_online_cpu(cpu) {
>                         handler =3D per_cpu_ptr(&plic_handlers, cpu);
>                         if (!handler->present) {
> -                               cpuhp_setup =3D false;
> +                               global_setup =3D false;
>                                 break;
>                         }
>                 }
> -               if (cpuhp_setup) {
> +
> +               if (global_setup) {
> +                       /* Find parent domain and register chained handle=
r */
> +                       domain =3D irq_find_matching_fwnode(riscv_get_int=
c_hwnode(), DOMAIN_BUS_ANY);
> +                       if (domain)
> +                               plic_parent_irq =3D irq_create_mapping(do=
main, RV_IRQ_EXT);
> +                       if (plic_parent_irq)
> +                               irq_set_chained_handler(plic_parent_irq, =
plic_handle_irq);
> +
>                         cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTI=
NG,
>                                           "irqchip/sifive/plic:starting",
>                                           plic_starting_cpu, plic_dying_c=
pu);
>                         register_syscore_ops(&plic_irq_syscore_ops);
> -                       plic_cpuhp_setup_done =3D true;
> +                       plic_global_setup_done =3D true;
>                 }
>         }
>
> --
> 2.44.1
>
>