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AJvYcCUj19vt5z1z8t+YzGHC9lkGRoZM0BzEMh0d2PZHKXGmUcafmufa/cLj71xCYXeyPPsPHPpm7WiXXwoUVW6vnItB+D0JcK/IlztirFHJ X-Gm-Message-State: AOJu0YwbgAgPScK6uTMW08eTUXQS0rAHLV4+RtjoIt0LuCpSbMaWYCPx gSvQdQJuMK+hgeQWrxTmb6c+oc7Hfm0umB9mShoYIWtagzDDfDUV X-Received: by 2002:ac2:5338:0:b0:525:32aa:443e with SMTP id 2adb3069b0e04-52b7d4282demr2002523e87.17.1717082339173; Thu, 30 May 2024 08:18:59 -0700 (PDT) Received: from andrea ([151.76.32.59]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a626c93872esm834551266b.86.2024.05.30.08.18.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 May 2024 08:18:58 -0700 (PDT) Date: Thu, 30 May 2024 17:18:43 +0200 From: Andrea Parri To: Alexandre Ghiti Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Leonardo Bras , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH -fixes v2] riscv: Fix fully ordered LR/SC xchg[8|16]() implementations Message-ID: References: <20240530145546.394248-1-alexghiti@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240530145546.394248-1-alexghiti@rivosinc.com> On Thu, May 30, 2024 at 04:55:46PM +0200, Alexandre Ghiti wrote: > The fully ordered versions of xchg[8|16]() using LR/SC lack the > necessary memory barriers to guarantee the order. > > Fix this by matching what is already implemented in the fully ordered > versions of cmpxchg() using LR/SC. > > Suggested-by: Andrea Parri > Reported-by: Andrea Parri > Closes: https://lore.kernel.org/linux-riscv/ZlYbupL5XgzgA0MX@andrea/T/#u > Fixes: a8ed2b7a2c13 ("riscv/cmpxchg: Implement xchg for variables of size 1 and 2") > Signed-off-by: Alexandre Ghiti Reviewed-by: Andrea Parri Thanks! Andrea