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Date: Thu, 30 May 2024 16:43:01 +0100
From: Conor Dooley <conor@kernel.org>
To: Chen-Yu Tsai <wenst@chromium.org>
Cc: Frank Binns <frank.binns@imgtec.com>,
	Matt Coster <matt.coster@imgtec.com>,
	Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
	Maxime Ripard <mripard@kernel.org>,
	Thomas Zimmermann <tzimmermann@suse.de>,
	Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
	David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>,
	dri-devel@lists.freedesktop.org, linux-clk@vger.kernel.org,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/6] dt-bindings: clock: mediatek: Add mt8173 mfgtop
Message-ID: <20240530-revisit-profanity-889f1bcae21a@spud>
References: <20240530083513.4135052-1-wenst@chromium.org>
 <20240530083513.4135052-2-wenst@chromium.org>
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On Thu, May 30, 2024 at 04:35:00PM +0800, Chen-Yu Tsai wrote:
> The MFG (GPU) block on the MT8173 has a small glue layer, named MFG_TOP
> in the datasheet, that contains clock gates, some power sequence signal
> delays, and other unknown registers that get toggled when the GPU is
> powered on.
>=20
> The clock gates are exposed as clocks provided by a clock controller,
> while the power sequencing bits are exposed as one singular power domain.
>=20
> Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
> ---
>  .../clock/mediatek,mt8173-mfgtop.yaml         | 71 +++++++++++++++++++
>  include/dt-bindings/clock/mt8173-clk.h        |  7 ++
>  2 files changed, 78 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt81=
73-mfgtop.yaml
>=20
> diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgt=
op.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.ya=
ml
> new file mode 100644
> index 000000000000..03c3c1f8cf75
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml
> @@ -0,0 +1,71 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +
> +$id: http://devicetree.org/schemas/clock/mediatek,mt8173-mfgtop.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek MT8173 MFG TOP controller
> +
> +maintainers:
> +  - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> +
> +description:
> +  The MFG TOP glue layer controls various signals going to the MFG (GPU)
> +  block on the MT8173.
> +
> +properties:
> +  compatible:
> +    const: mediatek,mt8173-mfgtop
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    minItems: 4

minItems is not needed when minItems =3D=3D maxItems.

> +    maxItems: 4
> +
> +  clock-names:
> +    items:
> +      - const: sys
> +      - const: mem
> +      - const: core
> +      - const: clk26m
> +
> +  power-domains:
> +    maxItems: 1
> +
> +  '#clock-cells':
> +    const: 1
> +
> +  '#power-domain-cells':
> +    const: 0
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - power-domains
> +  - '#clock-cells'
> +  - '#power-domain-cells'
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +        #include <dt-bindings/clock/mt8173-clk.h>
> +        #include <dt-bindings/power/mt8173-power.h>
> +
> +        mfgtop: clock-controller@13fff000 {

The label here is used, so drop it.

Otherwise,
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.

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