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[2001:14ba:a0c3:3a00::227]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2ea91bee55fsm185011fa.58.2024.05.30.10.04.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 May 2024 10:04:19 -0700 (PDT) Date: Thu, 30 May 2024 20:04:18 +0300 From: Dmitry Baryshkov To: Abel Vesa Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rajendra Nayak , Bryan O'Donoghue , Konrad Dybcio , Sibi Sankar , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] clk: qcom: gcc-x1e80100: Fix halt_check for all 3 USB PHY pipe clocks Message-ID: References: <20240530-x1e80100-clk-gcc-fix-halt-check-for-usb-phy-pipe-clks-v1-1-16c6f4dccbd5@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240530-x1e80100-clk-gcc-fix-halt-check-for-usb-phy-pipe-clks-v1-1-16c6f4dccbd5@linaro.org> On Thu, May 30, 2024 at 07:48:44PM +0300, Abel Vesa wrote: > Since the pipe clocks are fed by the QMP PHYs, they are not under the > GCC control, therefore the halt bit might not get. This will lead to Nit: might not get... set? cleared? > the clock driver reporting the clock as stuck, but that is inaccurate. > So instead of waiting for the halt bit to get set, just use the > HALT_DELAY flag. > > Fixes: 161b7c401f4b ("clk: qcom: Add Global Clock controller (GCC) driver for X1E80100") > Signed-off-by: Abel Vesa > --- > drivers/clk/qcom/gcc-x1e80100.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > Reviewed-by: Dmitry Baryshkov -- With best wishes Dmitry