Received-SPF: pass (google.com: domain of linux-kernel+bounces-196167-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) client-ip=147.75.80.249;
Precedence: bulk
MIME-Version: 1.0
References: <IA1PR20MB4953BA3638A0839FCB0EF86BBBF32@IA1PR20MB4953.namprd20.prod.outlook.com>
In-Reply-To: <IA1PR20MB4953BA3638A0839FCB0EF86BBBF32@IA1PR20MB4953.namprd20.prod.outlook.com>
From: Guo Ren <guoren@kernel.org>
Date: Fri, 31 May 2024 09:43:00 +0800
Message-ID: <CAJF2gTRu8WUkjOOzH4MZvinZv=0cgF988c7HyzP5jw0p3w+MWQ@mail.gmail.com>
Subject: Re: [PATCH] riscv: dts: thead: th1520: Add PMU event node
To: Inochi Amaoto <inochiama@outlook.com>
Cc: Jisheng Zhang <jszhang@kernel.org>, Fu Wei <wefu@redhat.com>, Rob Herring <robh@kernel.org>, 
	Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, 
	Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, 
	Albert Ou <aou@eecs.berkeley.edu>, linux-riscv@lists.infradead.org, 
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable

On Thu, May 30, 2024 at 7:19=E2=80=AFPM Inochi Amaoto <inochiama@outlook.co=
m> wrote:
>
> T-HEAD th1520 uses standard C910 chip and its pmu is already supported
> by OpenSBI.
>
> Add the pmu event description for T-HEAD th1520 SoC.
>
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> Link: https://www.xrvm.com/product/xuantie/4240217381324001280?spm=3Dxrvm=
27140568.0.0.7f979b29nzIa1m
> ---
>  arch/riscv/boot/dts/thead/th1520.dtsi | 81 +++++++++++++++++++++++++++
>  1 file changed, 81 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/=
thead/th1520.dtsi
> index d2fa25839012..3c9974062c20 100644
> --- a/arch/riscv/boot/dts/thead/th1520.dtsi
> +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
> @@ -122,6 +122,87 @@ l2_cache: l2-cache {
>                 };
>         };
>
> +       pmu {
> +               compatible =3D "riscv,pmu";
> +               riscv,event-to-mhpmcounters =3D
> +                       <0x00003 0x00003 0x0007fff8>,
> +                       <0x00004 0x00004 0x0007fff8>,
> +                       <0x00005 0x00005 0x0007fff8>,
> +                       <0x00006 0x00006 0x0007fff8>,
> +                       <0x00007 0x00007 0x0007fff8>,
> +                       <0x00008 0x00008 0x0007fff8>,
> +                       <0x00009 0x00009 0x0007fff8>,
> +                       <0x0000a 0x0000a 0x0007fff8>,
> +                       <0x10000 0x10000 0x0007fff8>,
> +                       <0x10001 0x10001 0x0007fff8>,
> +                       <0x10002 0x10002 0x0007fff8>,
> +                       <0x10003 0x10003 0x0007fff8>,
> +                       <0x10010 0x10010 0x0007fff8>,
> +                       <0x10011 0x10011 0x0007fff8>,
> +                       <0x10012 0x10012 0x0007fff8>,
> +                       <0x10013 0x10013 0x0007fff8>;
> +               riscv,event-to-mhpmevent =3D
> +                       <0x00003 0x00000000 0x00000001>,
> +                       <0x00004 0x00000000 0x00000002>,
> +                       <0x00006 0x00000000 0x00000006>,
> +                       <0x00005 0x00000000 0x00000007>,
> +                       <0x00007 0x00000000 0x00000008>,
> +                       <0x00008 0x00000000 0x00000009>,
> +                       <0x00009 0x00000000 0x0000000a>,
> +                       <0x0000a 0x00000000 0x0000000b>,
> +                       <0x10000 0x00000000 0x0000000c>,
> +                       <0x10001 0x00000000 0x0000000d>,
> +                       <0x10002 0x00000000 0x0000000e>,
> +                       <0x10003 0x00000000 0x0000000f>,
> +                       <0x10010 0x00000000 0x00000010>,
> +                       <0x10011 0x00000000 0x00000011>,
> +                       <0x10012 0x00000000 0x00000012>,
> +                       <0x10013 0x00000000 0x00000013>;
> +               riscv,raw-event-to-mhpmcounters =3D
> +                       <0x00000000 0x00000001 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x00000002 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x00000003 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x00000004 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x00000005 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x00000006 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x00000007 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x00000008 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x00000009 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x0000000a 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x0000000b 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x0000000c 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x0000000d 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x00000010 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x00000011 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x00000012 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x00000013 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x00000014 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x00000015 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x00000016 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x00000017 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x00000018 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x00000019 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x0000001a 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x0000001b 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x0000001c 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x0000001d 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x0000001e 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x0000001f 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x00000020 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x00000021 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x00000022 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x00000023 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x00000024 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x00000025 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x00000026 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x00000027 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x00000028 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x00000029 0xffffffff 0xffffffff 0x00=
07fff8>,
> +                       <0x00000000 0x0000002a 0xffffffff 0xffffffff 0x00=
07fff8>;
> +       };
> +
>         osc: oscillator {
>                 compatible =3D "fixed-clock";
>                 clock-output-names =3D "osc_24m";
> --
> 2.45.1
>
LGTM! Reviewed-by: Guo Ren <guoren@kernel.org>

--=20
Best Regards
 Guo Ren