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From: Alexander Stein <alexander.stein@ew.tq-group.com>
To: Shawn Guo <shawnguo@kernel.org>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, linux-arm-kernel@lists.infradead.org
Cc: Rasmus Villemoes <linux@rasmusvillemoes.dk>, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Esben Haabendal <esben@geanix.com>, Esben Haabendal <esben@geanix.com>
Subject: Re: [PATCH] ARM: dts: ls1021a: add QUICC Engine node
Date: Fri, 31 May 2024 08:32:44 +0200
Message-ID: <3380831.44csPzL39Z@steina-w>
Organization: TQ-Systems GmbH
In-Reply-To: <20240530-arm-ls1021a-qe-dts-v1-1-2eda23bdf8c5@geanix.com>
References: <20240530-arm-ls1021a-qe-dts-v1-1-2eda23bdf8c5@geanix.com>
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Hi Esben,

thanks for the patch.

Would you consider current converting into YAML format?

Am Donnerstag, 30. Mai 2024, 16:22:54 CEST schrieb Esben Haabendal:
> The LS1021A contains a QUICC Engine Block, so add a node to device
> tree describing that.
>=20
> Signed-off-by: Esben Haabendal <esben@geanix.com>
> ---
>  arch/arm/boot/dts/nxp/ls/ls1021a.dtsi | 51 +++++++++++++++++++++++++++++=
++++++
>  1 file changed, 51 insertions(+)
>=20
> diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi b/arch/arm/boot/dts/nx=
p/ls/ls1021a.dtsi
> index e86998ca77d6..ff7be69acdd5 100644
> --- a/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi
> +++ b/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi
> @@ -460,6 +460,57 @@ gpio3: gpio@2330000 {
>  			#interrupt-cells =3D <2>;
>  		};
> =20
> +		uqe: uqe@2400000 {
> +			#address-cells =3D <1>;
> +			#size-cells =3D <1>;
> +			device_type =3D "qe";
> +			compatible =3D "fsl,qe", "simple-bus";
> +			ranges =3D <0x0 0x0 0x2400000 0x40000>;
> +			reg =3D <0x0 0x2400000 0x0 0x480>;

Properties please in this order:
* compatible
* reg
* #address-cells
* #size-cells
* ranges
* device_type

> +			brg-frequency =3D <150000000>;
> +			bus-frequency =3D <300000000>;

Mh, aren't these values depending on your actual RCW configuration?

> +			fsl,qe-num-riscs =3D <1>;
> +			fsl,qe-num-snums =3D <28>;

Current bindings defines:
> fsl,qe-snums: This property has to be specified as '/bits/ 8' value,
>   defining the array of serial number (SNUM) values for the virtual
>   threads.

So '/bits/ 8' is missing.

> +			qeic: qeic@80 {
> +				compatible =3D "fsl,qe-ic";
> +				reg =3D <0x80 0x80>;
> +				#address-cells =3D <0>;
> +				interrupt-controller;
> +				#interrupt-cells =3D <1>;
> +				interrupts =3D <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
> +					      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			ucc@2000 {
> +				cell-index =3D <1>;
> +				reg =3D <0x2000 0x200>;
> +				interrupts =3D <32>;
> +				interrupt-parent =3D <&qeic>;

Move cell-index to last position.

> +			};
> +
> +			ucc@2200 {
> +				cell-index =3D <3>;
> +				reg =3D <0x2200 0x200>;
> +				interrupts =3D <34>;
> +				interrupt-parent =3D <&qeic>;

Same here.

> +			};
> +
> +			muram@10000 {
> +				#address-cells =3D <1>;
> +				#size-cells =3D <1>;
> +				compatible =3D "fsl,qe-muram", "fsl,cpm-muram";
> +				ranges =3D <0x0 0x10000 0x6000>;

Node address but no 'reg' property? I have no idea if this is okay.
Also compatible (and possibly reg) first.

Thanks and best regards.
Alexander

> +				data-only@0 {
> +					compatible =3D "fsl,qe-muram-data",
> +					"fsl,cpm-muram-data";
> +					reg =3D <0x0 0x6000>;
> +				};
> +			};
> +		};
> +
>  		lpuart0: serial@2950000 {
>  			compatible =3D "fsl,ls1021a-lpuart";
>  			reg =3D <0x0 0x2950000 0x0 0x1000>;
>=20
> ---
> base-commit: 1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0
> change-id: 20240530-arm-ls1021a-qe-dts-093381110793
>=20
> Best regards,
>=20


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