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d="scan'208";a="41014389" Received: from smile.fi.intel.com ([10.237.72.54]) by orviesa003.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2024 01:34:08 -0700 Received: from andy by smile.fi.intel.com with local (Exim 4.97) (envelope-from ) id 1sCxi8-0000000CPyf-1hVQ; Fri, 31 May 2024 11:34:04 +0300 Date: Fri, 31 May 2024 11:34:03 +0300 From: Andy Shevchenko To: Douglas Anderson Cc: Greg Kroah-Hartman , Jiri Slaby , linux-arm-msm@vger.kernel.org, John Ogness , Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= , Tony Lindgren , Stephen Boyd , linux-serial@vger.kernel.org, Yicong Yang , Johan Hovold , linux-kernel@vger.kernel.org, Bjorn Andersson , Konrad Dybcio , Thomas Gleixner , Vijaya Krishna Nivarthi Subject: Re: [PATCH v2 2/7] serial: qcom-geni: Fix the timeout in qcom_geni_serial_poll_bit() Message-ID: References: <20240530224603.730042-1-dianders@chromium.org> <20240530154553.v2.2.I3e1968bbeee67e28fd4e15509950805b6665484a@changeid> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240530154553.v2.2.I3e1968bbeee67e28fd4e15509950805b6665484a@changeid> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo On Thu, May 30, 2024 at 03:45:54PM -0700, Douglas Anderson wrote: > The qcom_geni_serial_poll_bit() is supposed to be able to be used to > poll a bit that's will become set when a TX transfer finishes. Because > of this it tries to set its timeout based on how long the UART will > take to shift out all of the queued bytes. There are two problems > here: > 1. There appears to be a hidden extra word on the firmware side which > is the word that the firmware has already taken out of the FIFO and > is currently shifting out. We need to account for this. > 2. The timeout calculation was assuming that it would only need 8 bits > on the wire to shift out 1 byte. This isn't true. Typically 10 bits > are used (8 data bits, 1 start and 1 stop bit), but as much as 13 > bits could be used (14 if we allowed 9 bits per byte, which we > don't). > > The too-short timeout was seen causing problems in a future patch > which more properly waited for bytes to transfer out of the UART > before cancelling. .. > + /* > + * Add 1 to tx_fifo_depth to account for the hidden register > + * on the firmware side that can hold a word. > + */ > + max_queued_bytes = > + DIV_ROUND_UP((port->tx_fifo_depth + 1) * port->tx_fifo_width, > + BITS_PER_BYTE); BITS_TO_BYTES() .. > - timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500; > + timeout_us = ((max_queued_bits * USEC_PER_SEC) / baud) + 500; Too many parentheses. (The outer ones can be dropped. -- With Best Regards, Andy Shevchenko