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From: Qingfang Deng <dqfext@gmail.com>
To: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Samuel Holland <samuel.holland@sifive.com>,
	Qingfang Deng <qingfang.deng@siflower.com.cn>,
	Eric Chan <ericchancf@google.com>,
	Andrea Parri <parri.andrea@gmail.com>,
	linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: [PATCH] RISC-V: Implement ioremap_wc/wt
Date: Fri, 31 May 2024 18:04:06 +0800
Message-Id: <20240531100407.282-1-dqfext@gmail.com>
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From: Qingfang Deng <qingfang.deng@siflower.com.cn>

Currently on RISC-V, ioremap_wc/wt uses the default ioremap
implementation, which maps the memory as strongly-ordered non-cacheable
IO memory on systems with Svpbmt.

To improve performance, map the memory as weakly-ordered non-cacheable
normal memory.

Signed-off-by: Qingfang Deng <qingfang.deng@siflower.com.cn>
---
 arch/riscv/include/asm/io.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
index 1c5c641075d2..582503e0f508 100644
--- a/arch/riscv/include/asm/io.h
+++ b/arch/riscv/include/asm/io.h
@@ -133,6 +133,14 @@ __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw())
 #define outsq(addr, buffer, count) __outsq(PCI_IOBASE + (addr), buffer, count)
 #endif
 
+#ifdef CONFIG_MMU
+#define ioremap_wc(addr, size) \
+	ioremap_prot((addr), (size), \
+		     (_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_NOCACHE)
+
+#define ioremap_wt ioremap_wc
+#endif
+
 #include <asm-generic/io.h>
 
 #ifdef CONFIG_MMU
-- 
2.34.1