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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Just like most of clock controllers, the SDM845 Display clock controller is also some variant of standard Qualcomm GCC, so reference common qcom,gcc.yaml schema to simplify the binding and unify it with others. Signed-off-by: Krzysztof Kozlowski --- .../bindings/clock/qcom,sdm845-dispcc.yaml | 20 ++++---------------- 1 file changed, 4 insertions(+), 16 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml index 719844d7ea11..220f4004f7fd 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml @@ -46,28 +46,16 @@ properties: - const: dp_link_clk_divsel_ten - const: dp_vco_divided_clk_src_mux - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - required: - compatible - - reg - clocks - clock-names - - '#clock-cells' - - '#reset-cells' - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | -- 2.43.0