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AJvYcCWxvf4JH2ZMROmeZBBtMbLJ2HWZUXQICyLdjLAASghMx4xwg7dBPtbfNon7YqKH39uCXly1TTGMpgimNR9r2lh4jawhviAHPlGJDTffZC+HHVJioC+D/A6xuVXy4wzjGKl0MhZYXc3vC2B/RtDfpzovC3Ez1oy/1Xh5xuvh37GNdnAGOw== X-Gm-Message-State: AOJu0YxJIPQv6rfKUMt57XRIYlJ6qB7FQh58Gx3mnXLVHn/0OhF/HxmP b4q2KO/sOXyvi9id3/v+jt1X4zA2HsXHvfZzSag0N/njmtOFyyvbdrnCGbBb7qsuSLgyEdI8gxh UchC8Xz8LDDaWbzPHMXyayWZgFyM= X-Received: by 2002:a17:90b:2282:b0:2bd:fa57:b361 with SMTP id 98e67ed59e1d1-2c1dc56fce1mr1799546a91.11.1717165510580; Fri, 31 May 2024 07:25:10 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240530083513.4135052-1-wenst@chromium.org> <20240530083513.4135052-4-wenst@chromium.org> In-Reply-To: From: Adam Ford Date: Fri, 31 May 2024 09:24:56 -0500 Message-ID: Subject: Re: [PATCH 3/6] dt-bindings: gpu: powervr-rogue: Add MediaTek MT8173 GPU To: Frank Binns Cc: "matthias.bgg@gmail.com" , "tzimmermann@suse.de" , Matt Coster , "sboyd@kernel.org" , "robh@kernel.org" , "krzk+dt@kernel.org" , "maarten.lankhorst@linux.intel.com" , "wenst@chromium.org" , "mripard@kernel.org" , "conor+dt@kernel.org" , "angelogioacchino.delregno@collabora.com" , "dri-devel@lists.freedesktop.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "airlied@gmail.com" , "linux-arm-kernel@lists.infradead.org" , "linux-mediatek@lists.infradead.org" , "daniel@ffwll.ch" , "linux-clk@vger.kernel.org" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, May 31, 2024 at 8:37=E2=80=AFAM Frank Binns wrote: > > Hi ChenYu, > > On Thu, 2024-05-30 at 16:35 +0800, Chen-Yu Tsai wrote: > > The MediaTek MT8173 comes with a PowerVR Rogue GX6250, which is one > > of the Series6XT GPUs, another sub-family of the Rogue family. > > I've added Adam Ford who sent out some DT related patches [1] for the Ren= esas > variant of GX6250 and the GX6650 (another Series6XT GPU). > Thanks for including me. > > > > This was part of the very first few versions of the PowerVR submission, > > but was later dropped. The compatible string has been updated to follow > > the new naming scheme adopted for the AXE series. > > > > In a previous iteration of the PowerVR binding submission [1], the > > number of clocks required for the 6XT family was mentioned to be > > always 3. This is also reflected here. > > > > [1] https://lore.kernel.org/dri-devel/6eeccb26e09aad67fb30ffcd523c793a4= 3c79c2a.camel@imgtec.com/ > > > > Signed-off-by: Chen-Yu Tsai > > --- > > .../bindings/gpu/img,powervr-rogue.yaml | 24 +++++++++++++++---- > > 1 file changed, 20 insertions(+), 4 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.ya= ml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml > > index 256e252f8087..48aa205b66b4 100644 > > --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml > > +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml > > @@ -12,10 +12,17 @@ maintainers: > > > > properties: > > compatible: > > - items: > > - - enum: > > - - ti,am62-gpu > > - - const: img,img-axe # IMG AXE GPU model/revision is fully disco= verable > > + oneOf: > > + - items: > > + - enum: > > + - mediatek,mt8173-gpu > > + # PowerVR 6XT GPU model/revision is fully discoverable > > + - const: img,powervr-6xt > > + - items: > > + - enum: > > + - ti,am62-gpu > > + # IMG AXE GPU model/revision is fully discoverable > > + - const: img,img-axe > > The Series6XT GPU models have differing numbers of power domains (either = 2, 4 or > 5). Whereas, the AXE GPUs have a single power domain, so I assume there s= hould > be a related change here. > > The GX6250 has two power domains (lets call them A and B). There's a cons= traint > that if domain B is powered then domain A must also be powered. > > In patch 6 [2] it's setting the power domain to MT8173_POWER_DOMAIN_MFG, = which I > believe corresponds to power domain B. I assume this works because the MT= K power > controller driver is encoding the constraint above, meaning that when we = disable > or enable MT8173_POWER_DOMAIN_MFG it's also disabling/enabling MT8173_POW= ER_DOMA > IN_MFG_2D (domain A). > In the cover letter of this series, it was noted that the GPU enumerates, but it doesn' fully function yet. This is also the case for both of the Renesas variants I have been testing, and I was nicely asked to postpone my series until the driver was closer to being ready. Even if the driver isn't ready yet, it would be nice to move the bindings forward. adam > Thanks > Frank > > [1] https://lists.freedesktop.org/archives/dri-devel/2024-February/443548= html > [2] https://lists.freedesktop.org/archives/dri-devel/2024-May/455833.html > > > > > reg: > > maxItems: 1 > > @@ -56,6 +63,15 @@ allOf: > > properties: > > clocks: > > maxItems: 1 > > + - if: > > + properties: > > + compatible: > > + contains: > > + const: img,powervr-6xt > > + then: > > + properties: > > + clocks: > > + minItems: 3 > > > > examples: > > - |