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Date: Sat, 1 Jun 2024 23:23:39 +0100 (BST)
From: "Maciej W. Rozycki" <macro@orcam.me.uk>
To: Jiaxun Yang <jiaxun.yang@flygoat.com>
cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>, 
    Serge Semin <fancer.lancer@gmail.com>, 
    Daniel Lezcano <daniel.lezcano@linaro.org>, 
    Thomas Gleixner <tglx@linutronix.de>, linux-mips@vger.kernel.org, 
    linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/7] MIPS: csrc-r4k: Refine rating computation
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On Sat, 11 May 2024, Jiaxun Yang wrote:

> Increase frequency addend dividend to 100000000 (10MHz) to

 The value of 100000000 is AFAICT 100MHz.

> diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c
> index edc4afc080fa..262896871351 100644
> --- a/arch/mips/kernel/csrc-r4k.c
> +++ b/arch/mips/kernel/csrc-r4k.c
> @@ -111,7 +111,8 @@ int __init init_r4k_clocksource(void)
>  		return -ENXIO;
>  
>  	/* Calculate a somewhat reasonable rating value */
> -	clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
> +	clocksource_mips.rating = 200;
> +	clocksource_mips.rating += clamp(mips_hpt_frequency / 100000000, 0, 99);

 And FAOD the code change does match it.

  Maciej