Received-SPF: pass (google.com: domain of linux-kernel+bounces-198576-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) client-ip=147.75.199.223;
Date: Mon, 3 Jun 2024 12:34:27 +0900
From: Jung Daehwan <dh10.jung@samsung.com>
To: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Rob Herring
	<robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley
	<conor+dt@kernel.org>, Thinh Nguyen <Thinh.Nguyen@synopsys.com>, Mathias
	Nyman <mathias.nyman@intel.com>, Felipe Balbi <balbi@kernel.org>, "open
 list:USB SUBSYSTEM" <linux-usb@vger.kernel.org>, "open list:OPEN FIRMWARE
 AND FLATTENED DEVICE TREE BINDINGS" <devicetree@vger.kernel.org>, open list
	<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 3/5] dt-bindings: usb: xhci: Add
 'write-64-hi-lo-quirk' quirk
Message-ID: <20240603033427.GB23593@ubuntu>
Precedence: bulk
MIME-Version: 1.0
In-Reply-To: <bcbff3b2-c5ae-4a95-aa36-f9b88a97e72c@kernel.org>
User-Agent: Mutt/1.5.24 (2015-08-30)
Content-Type: multipart/mixed;
	boundary="----CGP_Yo4KSd1.GMH1id3MjqccfDy5Ep7f4Yd1jhLawOabyReQ=_377ca_"
CMS-TYPE: 102P
DLP-Filter: Pass
References: <1717135657-120818-1-git-send-email-dh10.jung@samsung.com>
	<CGME20240531060729epcas2p1df12dd3b14c5fa2fa0716f72010b3dbd@epcas2p1.samsung.com>
	<1717135657-120818-4-git-send-email-dh10.jung@samsung.com>
	<bcbff3b2-c5ae-4a95-aa36-f9b88a97e72c@kernel.org>

------CGP_Yo4KSd1.GMH1id3MjqccfDy5Ep7f4Yd1jhLawOabyReQ=_377ca_
Content-Type: text/plain; charset="us-ascii"
Content-Disposition: inline

On Fri, May 31, 2024 at 10:12:03AM +0200, Krzysztof Kozlowski wrote:
> On 31/05/2024 08:07, Daehwan Jung wrote:
> > xHCI specification 5.1 "Register Conventions" states that 64 bit
> > registers should be written in low-high order. All writing operations
> > in xhci is done low-high order following the spec.
> 
> What is high-low / low-high order? Are you talking about endianness?
> 

It's not about endianness. It means 64 bit is written by 2 of 32 bit.
It's when low-high / high-low order is needed.

> > 
> > Add a new quirk to support workaround for high-low order.
> 
> Why? If they should be written low-high, then why breaking the spec? Why
> this cannot be deduced from compatible?
> 

This quirk is for the controller that has a limitation in supporting
separate ERSTBA_HI and ERSTBA_LO programming.

I've copied below from other reply to tell why this is needed.

I've found out the limitation of Synopsys dwc3 controller. This can work
on Host mode using xHCI. A Register related to ERST should be written
high-low order not low-high order. Registers are always written low-high order
following xHCI spec.(64-bit written is done in each 2 of 32-bit)
That's why new quirk is needed for workaround. This quirk is used not in
dwc3 controller itself, but passed to xhci quirk eventually. That's because
this issue occurs in Host mode using xHCI.

> Which *upstream* hardware is affected?
>

dwc3 and xhci are affected.

Best Regards,
Jung Daehwan

> 
> 
> Best regards,
> Krzysztof
> 
> 
> 

------CGP_Yo4KSd1.GMH1id3MjqccfDy5Ep7f4Yd1jhLawOabyReQ=_377ca_
Content-Type: text/plain; charset="utf-8"


------CGP_Yo4KSd1.GMH1id3MjqccfDy5Ep7f4Yd1jhLawOabyReQ=_377ca_--