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Mon, 3 Jun 2024 06:57:33 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 55D6539FE5; Mon, 3 Jun 2024 06:57:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tIqpmvEh" Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A2A5376E6; Mon, 3 Jun 2024 06:57:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717397841; cv=none; b=tsogKyNaKA4p/qLHqMX1ZLPNL4d5WLOdTL2j2XlBgTBsUJ0kGahZ7mqHx6rMhk25K/3Xv3b5CjVo5kbDku7yznAv43etXfwQ4HVVpKyADCq6sA1BC/R5+/3F68OuUx198JPjXlrHcFG35T8eWzbHYvJfvlxNhh/W7aDwDXyRwIc= ARC-Message-Signature:i=1; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 03/06/2024 05:03, Jung Daehwan wrote: > On Fri, May 31, 2024 at 10:10:30AM +0200, Krzysztof Kozlowski wrote: >> On 31/05/2024 08:07, Daehwan Jung wrote: >>> Add a new quirk for dwc3 core to support writing high-low order. >> >> This does not tell me more. Could be OS property as well... please >> describe hardware and provide rationale why this is suitable for >> bindings (also cannot be deduced from compatible). >> >> > > Hi, > > I'm sorry I didn't describe it in dt-bindings patches. > It's described in cover-letter and other patches except in dt-bindings. > I will add it in next submission. > > I've found out the limitation of Synopsys dwc3 controller. This can work > on Host mode using xHCI. A Register related to ERST should be written > high-low order not low-high order. Registers are always written low-high order > following xHCI spec.(64-bit written is done in each 2 of 32-bit) > That's why new quirk is needed for workaround. This quirk is used not in > dwc3 controller itself, but passed to xhci quirk eventually. That's because > this issue occurs in Host mode using xHCI. > If there is only one register then you should just program it differently and it does not warrant quirk property. Best regards, Krzysztof