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From: Thomas Gleixner <tglx@linutronix.de>
To: Prabhakar <prabhakar.csengg@gmail.com>, Geert Uytterhoeven
 <geert+renesas@glider.be>, Rob Herring <robh@kernel.org>, Krzysztof
 Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, Magnus
 Damm <magnus.damm@gmail.com>
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
 linux-renesas-soc@vger.kernel.org, Prabhakar <prabhakar.csengg@gmail.com>,
 Biju Das <biju.das.jz@bp.renesas.com>, Lad Prabhakar
 <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH v4 2/2] irqchip/renesas-rzg2l: Add support for RZ/Five SoC
In-Reply-To: <20240430141438.132838-3-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20240430141438.132838-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <20240430141438.132838-3-prabhakar.mahadev-lad.rj@bp.renesas.com>
Date: Mon, 03 Jun 2024 14:40:06 +0200
Message-ID: <87bk4i6vyx.ffs@tglx>
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MIME-Version: 1.0
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On Tue, Apr 30 2024 at 15:14, Prabhakar wrote:
> +
> +static void rzfive_irqc_irq_disable(struct irq_data *d)
> +{
> +	rzfive_tint_irq_endisable(d, false);
> +	irq_chip_disable_parent(d);
> +}
> +
> +static void rzfive_irqc_irq_enable(struct irq_data *d)
> +{
> +	rzfive_tint_irq_endisable(d, true);
> +	irq_chip_enable_parent(d);
> +}

This looks wrong. Enable/disable should be symmetric vs. ordering, no?

Thanks,

        tglx