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[147.75.48.161]) by mx.google.com with ESMTPS id d9443c01a7336-1f67f27c061si16091705ad.31.2024.06.03.06.51.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jun 2024 06:51:54 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel+bounces-199222-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) client-ip=147.75.48.161; Authentication-Results: mx.google.com; arc=pass (i=1 spf=pass spfdomain=makrotopia.org); spf=pass (google.com: domain of linux-kernel+bounces-199222-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) smtp.mailfrom="linux-kernel+bounces-199222-linux.lists.archive=gmail.com@vger.kernel.org" Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sy.mirrors.kernel.org (Postfix) with ESMTPS id 4F696B27411 for ; Mon, 3 Jun 2024 13:32:26 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 21E0112E1D6; Mon, 3 Jun 2024 13:32:10 +0000 (UTC) Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A9F1212D1FA; Mon, 3 Jun 2024 13:32:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.142.180.65 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717421529; cv=none; b=c4/jIXYVhpoS+Eu5stzG53TJMtGNuxqFFucpLrzZWU01CZcd8SPs7c5B22vpUlP2F0Ih27rB0tdda6R600JZNS0fAYqO6oHh5VgAx3jgcYMp8WelPhrkC1h7puKa/WgVYB26GMDTRH0r7y/M6EzxGaa0aXMX+1tY9RM6QlWO5Wo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717421529; c=relaxed/simple; bh=i7qyliEW3tXAHVQUR36q8o9p80BoaaM8/W3VFHNn2Wc=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=gTg3c5bmGFsZcKZ5Jcs9if7Os55gMR8f7Mue9UOLLSSZwYnLbyCHXTeNQxDeT4nSTH5vj0L2I3PDhs9dNBoEAF7VikadId9qm2CHr0X3ZgbQpmdFXXLlMHGGgAuGGbIiZfJfBCDbvCSvdV+wVUHQeiRDzwjL2JJXghe5gWoHRRE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org; spf=pass smtp.mailfrom=makrotopia.org; arc=none smtp.client-ip=185.142.180.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=makrotopia.org Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.97.1) (envelope-from ) id 1sE7mv-000000001SM-47uV; Mon, 03 Jun 2024 13:31:50 +0000 Date: Mon, 3 Jun 2024 14:31:46 +0100 From: Daniel Golle To: "Russell King (Oracle)" Cc: Sky Huang , Andrew Lunn , Heiner Kallweit , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Qingfang Deng , Matthias Brugger , AngeloGioacchino Del Regno , linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Steven Liu Subject: Re: [PATCH net-next v6 5/5] net: phy: add driver for built-in 2.5G ethernet PHY on MT7988 Message-ID: References: <20240603121834.27433-1-SkyLake.Huang@mediatek.com> <20240603121834.27433-6-SkyLake.Huang@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Mon, Jun 03, 2024 at 02:25:01PM +0100, Russell King (Oracle) wrote: > On Mon, Jun 03, 2024 at 08:18:34PM +0800, Sky Huang wrote: > > Add support for internal 2.5Gphy on MT7988. This driver will load > > necessary firmware, add appropriate time delay and figure out LED. > > Also, certain control registers will be set to fix link-up issues. > > Based on our previous discussion, it may be worth checking in the > .config_init() method whether phydev->interface is one of the > PHY interface modes that this PHY supports. As I understand from one > of your previous emails, the possibilities are XGMII, USXGMII or > INTERNAL. Thus: > > > +static int mt798x_2p5ge_phy_config_init(struct phy_device *phydev) > > +{ > > + struct pinctrl *pinctrl; > > + int ret; > > /* Check that the PHY interface type is compatible */ > if (phydev->interface != PHY_INTERFACE_MODE_INTERNAL && > phydev->interface != PHY_INTERFACE_MODE_XGMII && > phydev->interface != PHY_INTERFACE_MODE_USXGMII) > return -ENODEV; The PHY is built-into the SoC, and as such the connection type should always be "internal". The PHY does not exist as dedicated IC, only as built-in part of the MT7988 SoC.