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Date: Mon, 3 Jun 2024 18:00:49 +0100
From: Daniel Golle <daniel@makrotopia.org>
To: "Russell King (Oracle)" <linux@armlinux.org.uk>
Cc: Sky Huang <SkyLake.Huang@mediatek.com>, Andrew Lunn <andrew@lunn.ch>,
	Heiner Kallweit <hkallweit1@gmail.com>,
	"David S. Miller" <davem@davemloft.net>,
	Eric Dumazet <edumazet@google.com>,
	Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
	Qingfang Deng <dqfext@gmail.com>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
	linux-kernel@vger.kernel.org, netdev@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-mediatek@lists.infradead.org,
	Steven Liu <Steven.Liu@mediatek.com>
Subject: Re: [PATCH net-next v6 5/5] net: phy: add driver for built-in 2.5G
 ethernet PHY on MT7988
Message-ID: <Zl32waW34yTiuF9u@makrotopia.org>
References: <20240603121834.27433-1-SkyLake.Huang@mediatek.com>
 <20240603121834.27433-6-SkyLake.Huang@mediatek.com>
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 <Zl3Fwoiv1bJlGaQZ@makrotopia.org>
 <Zl3IGN5ZHCQfQfmt@shell.armlinux.org.uk>
 <Zl3Yo3dwQlXEfP3i@makrotopia.org>
 <Zl3lkIDqnt4JD//u@shell.armlinux.org.uk>
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On Mon, Jun 03, 2024 at 04:47:28PM +0100, Russell King (Oracle) wrote:
> On Mon, Jun 03, 2024 at 03:52:19PM +0100, Daniel Golle wrote:
> > On Mon, Jun 03, 2024 at 02:41:44PM +0100, Russell King (Oracle) wrote:
> > > On Mon, Jun 03, 2024 at 02:31:46PM +0100, Daniel Golle wrote:
> > > > On Mon, Jun 03, 2024 at 02:25:01PM +0100, Russell King (Oracle) wrote:
> > > > > On Mon, Jun 03, 2024 at 08:18:34PM +0800, Sky Huang wrote:
> > > > > > Add support for internal 2.5Gphy on MT7988. This driver will load
> > > > > > necessary firmware, add appropriate time delay and figure out LED.
> > > > > > Also, certain control registers will be set to fix link-up issues.
> > > > > 
> > > > > Based on our previous discussion, it may be worth checking in the
> > > > > .config_init() method whether phydev->interface is one of the
> > > > > PHY interface modes that this PHY supports. As I understand from one
> > > > > of your previous emails, the possibilities are XGMII, USXGMII or
> > > > > INTERNAL. Thus:
> > > > > 
> > > > > > +static int mt798x_2p5ge_phy_config_init(struct phy_device *phydev)
> > > > > > +{
> > > > > > +	struct pinctrl *pinctrl;
> > > > > > +	int ret;
> > > > > 
> > > > > 	/* Check that the PHY interface type is compatible */
> > > > > 	if (phydev->interface != PHY_INTERFACE_MODE_INTERNAL &&
> > > > > 	    phydev->interface != PHY_INTERFACE_MODE_XGMII &&
> > > > > 	    phydev->interface != PHY_INTERFACE_MODE_USXGMII)
> > > > > 		return -ENODEV;
> > > > 
> > > > The PHY is built-into the SoC, and as such the connection type should
> > > > always be "internal". The PHY does not exist as dedicated IC, only
> > > > as built-in part of the MT7988 SoC.
> > > 
> > > That's not how it was described to me by Sky.
> > > 
> > > If what you say is correct, then the implementation of
> > > mt798x_2p5ge_phy_get_rate_matching() which checks for interface modes
> > > other than INTERNAL is not correct. Also it means that config_init()
> > > should not permit anything but INTERNAL.
> > 
> > The way the PHY is connected to the MAC *inside the chip* is XGMII
> > according the MediaTek. So call it "internal" or "xgmii", however, up to
> > my knowledge it's a fact that there is **only one way** this PHY is
> > connected and used, and that is being an internal part of the MT7988 SoC.
> > 
> > Imho, as there are no actual XGMII signals exposed anywhere I'd use
> > "internal" to describe the link between MAC and PHY (which are both
> > inside the same chip package).
> 
> I don't care what gets decided about what's acceptable for the PHY to
> accept, just that it checks for the acceptable modes in .config_init()
> and the .get_rate_matching() method is not checking for interface
> modes that are not permitted.

What I meant to express is that there is no need for such a check, also
not in config_init. There is only one way and one MAC-side interface mode
to operate that PHY, so the value will anyway not be considered anywhere
in the driver.