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Date: Tue, 4 Jun 2024 10:51:36 +0530
From: Siddharth Vadapalli <s-vadapalli@ti.com>
To: Andrew Davis <afd@ti.com>
CC: Siddharth Vadapalli <s-vadapalli@ti.com>, <nm@ti.com>, <vigneshr@ti.com>,
        <kristo@kernel.org>, <robh@kernel.org>, <krzk+dt@kernel.org>,
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        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>, <u-kumar1@ti.com>,
        <danishanwar@ti.com>, <srk@ti.com>
Subject: Re: [PATCH v4 6/7] arm64: dts: ti: k3-j722s-main: Add SERDES and
 PCIe support
Message-ID: <4c29a5d9-d7ec-4175-b726-c41e2711ac0f@ti.com>
References: <20240601121554.2860403-1-s-vadapalli@ti.com>
 <20240601121554.2860403-7-s-vadapalli@ti.com>
 <147d58a6-0cad-47b6-a069-755f835a77e9@ti.com>
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In-Reply-To: <147d58a6-0cad-47b6-a069-755f835a77e9@ti.com>

On Mon, Jun 03, 2024 at 09:17:43AM -0500, Andrew Davis wrote:
> On 6/1/24 7:15 AM, Siddharth Vadapalli wrote:
> > J722S SoC has two instances of SERDES namely SERDES0 and SERDES1 and one
> > instance of PCIe namely PCIe0. Both SERDES0 and SERDES1 are single lane
> > SERDES. The PCIe0 instance of PCIe is a Gen3 single lane PCIe controller.
> > 

[...]

> > +
> > +		serdes0: serdes@f000000 {
> > +			compatible = "ti,j721e-serdes-10g";
> > +			reg = <0x0f000000 0x00010000>;
> > +			reg-names = "torrent_phy";
> > +			resets = <&serdes_wiz0 0>;
> > +			reset-names = "torrent_reset";
> > +			clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
> > +				 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
> > +			clock-names = "refclk", "phy_en_refclk";
> > +			assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
> > +					  <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
> > +					  <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
> > +			assigned-clock-parents = <&k3_clks 279 1>,
> > +						 <&k3_clks 279 1>,
> > +						 <&k3_clks 279 1>;
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			#clock-cells = <1>;
> > +
> > +			status = "disabled"; /* Needs lane config */
> 
> Does the other SERDES (serdes1) not need this config? It looks like
> it does in the board file.. If so disable it too.

The "lane config" being referred to here is set by the "serdes_ln_ctrl"
mux. The idle-states being set in the board file match the reset values
of the mux, so it is not technically necessary to disable it. However, I
will go ahead and disable SERDES1 as well and enable it in the board file
in the v5 series. Thank you for the review.

[...]

Regards,
Siddharth.