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AJvYcCXLEATOwVkKg4mF2/IAGt2pXnwom767U9lIKuoPg1uMma/2bu+zfTyM67eCGXv4TFlfkvltZtphKMd8p2xpHB7ukOXYiBgWgg25YZ1X X-Gm-Message-State: AOJu0YxuR/lC4D8fRGbyhdWznb1xZjg6hZBhkTpURcDratVX130CW/2A 1Bt/Alffh+9BZA6J0Kjpln2rhPZiNr7hXnCyA4SyiuK4TZmlHUN4BhYfdSpW9kiE2MZaTTGqlUA CUGrAAO3ly3EHA2/FuknBltJX+J5dzAy3HHA= X-Received: by 2002:a17:906:2b0e:b0:a68:f5fe:ac8a with SMTP id a640c23a62f3a-a68f5feacc4mr404643666b.64.1717492570557; Tue, 04 Jun 2024 02:16:10 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240523211437.2839942-1-jwylder@google.com> <37abbb4e-cac4-4278-98fb-0af75e5b3ef4@sirena.org.uk> In-Reply-To: <37abbb4e-cac4-4278-98fb-0af75e5b3ef4@sirena.org.uk> From: Andy Shevchenko Date: Tue, 4 Jun 2024 12:15:33 +0300 Message-ID: Subject: Re: [PATCH v2] regmap-i2c: Subtract reg size from max_write To: Mark Brown Cc: Jim Wylder , Greg Kroah-Hartman , "Rafael J. Wysocki" , kernel-team@android.com, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Mon, Jun 3, 2024 at 3:08=E2=80=AFPM Mark Brown wrot= e: > > On Sun, Jun 02, 2024 at 10:29:07AM +0300, Andy Shevchenko wrote: > > > > (bus->max_raw_write =3D=3D 0 || bus->max_raw_write > = quirks->max_write_len)) > > > - max_write =3D quirks->max_write_len; > > > + max_write =3D quirks->max_write_len - > > > + (config->reg_bits + config->pad_bits) / B= ITS_PER_BYTE; > > > Interesting. regmap-spi does this slightly differently, i.e. reg/8 + pa= d/8. > > I'm wondering which one is more correct (potential off-by-one I suppose= ). > > The above seems more correct if we have less than a full byte of padding. Hmm... So, if we have bits pad x/8+y/8 (x+y)/8 4..7 0..3 0 0 // x + y from 4 up to 7 4..7 4..7 0 1 // x + y from 8 up to 11 4..7 8..11 1 1 // x + y from 12 up to 15 8..15 0..7 1 1 // x + y from 8 up to 15 8..15 8..15 2 2 // x + y from 16 up to 23 The only difference AFAICS is the case 2. Do we need to patch regmap SPI for that? I think SPI just works since we don't really have devices that use less than 8 bits per register, and hence we never enter into such a case (while I2C is naturally using 7-bit addresses). --=20 With Best Regards, Andy Shevchenko