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([2a00:f41:909a:a11e:a035:2af2:8d85:1f72]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a68b71450c1sm471790866b.152.2024.06.04.05.00.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 04 Jun 2024 05:00:19 -0700 (PDT) Message-ID: Date: Tue, 4 Jun 2024 14:00:10 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] arm64: dts: qcom: x1e80100: Make the PCIe 6a PHY support 4 lanes mode To: Johan Hovold , Abel Vesa Cc: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Rajendra Nayak , Sibi Sankar , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20240531-x1e80100-dts-fixes-pcie6a-v1-0-1573ebcae1e8@linaro.org> <20240531-x1e80100-dts-fixes-pcie6a-v1-2-1573ebcae1e8@linaro.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 6/3/24 14:52, Johan Hovold wrote: [...] > > As I just mentioned in my reply on the PHY patch, this does not seem to > work on the CRD were the link still come up as 2-lane (also with the > clocks fixed): > > qcom-pcie 1bf8000.pci: PCIe Gen.4 x2 link up > > So something appears to be wrong here or in the PHY changes. Is the device on the other end x4-capable? Or does it not matter in this log line? Konrad