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Date: Tue, 4 Jun 2024 14:47:30 +0200
From: Johan Hovold <johan@kernel.org>
To: Abel Vesa <abel.vesa@linaro.org>
Cc: Vinod Koul <vkoul@kernel.org>,
	Kishon Vijay Abraham I <kishon@kernel.org>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>, linux-arm-msm@vger.kernel.org,
	linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] phy: qcom: qmp-pcie: Add X1E80100 Gen4 4-lane mode
 support
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References: <20240531-x1e80100-phy-add-gen4x4-v1-0-5c841dae7850@linaro.org>
 <20240531-x1e80100-phy-add-gen4x4-v1-2-5c841dae7850@linaro.org>
 <Zl27FJVU_YHokCiD@hovoldconsulting.com>
 <Zl8H0KOrfuF91kpZ@linaro.org>
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On Tue, Jun 04, 2024 at 03:25:52PM +0300, Abel Vesa wrote:
> On 24-06-03 14:46:12, Johan Hovold wrote:

> > I tried this patch along with the DT changes and the link on the CRD
> > still comes up as 2-lane:
> > 
> > 	qcom-pcie 1bf8000.pci: PCIe Gen.4 x2 link up
> > 
> > so something appears to be wrong here. (I noticed the same with your
> > next branch last week.)
> > 
> > How did you test this? Does the link actually come up as 4-lane for you?
> 
> This is the PHY part. The controller needs some changes as well.

Are you sure? It wasn't needed on sc8280xp (except for updating
num-lanes in DT).

> Yes, as of yet, I'm not able to bring the link up in 4-lanes mode.

Thanks for confirming.

> This however doesn't mean the PHY sequence is incorrect.

Not necessarily, but it means it hasn't been fully tested and that it
could potentially be the reason for the failed x4 link up.

Johan