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([2a00:f41:909a:a11e:a035:2af2:8d85:1f72]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57a81f1dbd9sm1152023a12.93.2024.06.04.05.38.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 04 Jun 2024 05:38:43 -0700 (PDT) Message-ID: <402aa998-8b3c-4c3c-8dcb-f128b6ddac46@linaro.org> Date: Tue, 4 Jun 2024 14:38:40 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] arm64: dts: qcom: x1e80100: Make the PCIe 6a PHY support 4 lanes mode To: Johan Hovold Cc: Abel Vesa , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Rajendra Nayak , Sibi Sankar , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20240531-x1e80100-dts-fixes-pcie6a-v1-0-1573ebcae1e8@linaro.org> <20240531-x1e80100-dts-fixes-pcie6a-v1-2-1573ebcae1e8@linaro.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 6/4/24 14:20, Johan Hovold wrote: > On Tue, Jun 04, 2024 at 02:00:10PM +0200, Konrad Dybcio wrote: >> On 6/3/24 14:52, Johan Hovold wrote: > >>> As I just mentioned in my reply on the PHY patch, this does not seem to >>> work on the CRD were the link still come up as 2-lane (also with the >>> clocks fixed): >>> >>> qcom-pcie 1bf8000.pci: PCIe Gen.4 x2 link up >>> >>> So something appears to be wrong here or in the PHY changes. >> >> Is the device on the other end x4-capable? Or does it not matter in >> this log line? > > Yes, of course. It's the CRD as I wrote above, and you can tell from > other log entries: > > pci 0007:01:00.0: 31.506 Gb/s available PCIe bandwidth, limited by 16.0 GT/s PCIe x2 link at 0007:00:00.0 (capable of 63.012 Gb/s with 16.0 GT/s PCIe x4 link) > > lspci and what Windows reports. Ok, good. I was scared of double-sourcing of parts that are not identical in spec.. [1] suggests this wasn't ever achieved.. which makes the cover letter of this series a bit misleading.. What does the TCSR check return? If 0, can you hardcode it to 1 and see if the link comes up at x4? Konrad [1] https://lore.kernel.org/all/Zl8H0KOrfuF91kpZ@linaro.org/