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X-MS-Exchange-CrossTenant-Id: 4e2c6054-71cb-48f1-bd6c-3a9705aca71b X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Pdh6PrPUsAXojzk6h2bCfnSPTLn+p0DMjzcC0QXc7DyiRLJm/v9ial4qHHWNGbBte+MYIF6/E6+O1+2ZrpLsmT7n57lEvXmkWmbnD/ADNHI= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN6PR10MB8024 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-04_05,2024-06-04_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxlogscore=999 phishscore=0 adultscore=0 bulkscore=0 spamscore=0 malwarescore=0 mlxscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000 definitions=main-2406040107 X-Proofpoint-ORIG-GUID: RrU9zoW4nn5gAQ4GMLiX7iT8PtBMjkD2 X-Proofpoint-GUID: RrU9zoW4nn5gAQ4GMLiX7iT8PtBMjkD2 On 6/4/2024 9:16 AM, Ravi Bangoria wrote: >>>>> Events can be deleted and the entry can be NULL. >>>> Can you please also explain "how". >>> It looks like x86_pmu_stop() is clearing the bit in active_mask and setting the events entry to NULL (and doing it in the correct order) for the same events index that amd_pmu_enable_all() is trying to enable. >>>>> Check event for NULL in amd_pmu_enable_all() before enable to avoid a GPF. >>>>> This appears to be an AMD only issue. >>>>> >>>>> Syzkaller reported a GPF in amd_pmu_enable_all. >>>> Can you please provide a bug report link? Also, any reproducer? >>> The Syzkaller reproducer can be found in this link: >>> https://lore.kernel.org/netdev/CAMt6jhyec7-TSFpr3F+_ikjpu39WV3jnCBBGwpzpBrPx55w20g@mail.gmail.com/T/#u >>>>> @@ -760,7 +760,8 @@ static void amd_pmu_enable_all(int added) >>>>>           if (!test_bit(idx, cpuc->active_mask)) >>>>>               continue; >>>>>   -        amd_pmu_enable_event(cpuc->events[idx]); >>>>> +        if (cpuc->events[idx]) >>>>> +            amd_pmu_enable_event(cpuc->events[idx]); >>>> What if cpuc->events[idx] becomes NULL after if (cpuc->events[idx]) but >>>> before amd_pmu_enable_event(cpuc->events[idx])? >>> Good question, but the crash has not reproduced with the proposed fix in hours of testing. It usually reproduces within minutes without the fix. >> Also, a similar fix is done in __intel_pmu_enable_all() in arch/x86/events/intel/core.c except that a WARN_ON_ONCE is done as well. >> See: https://elixir.bootlin.com/linux/v6.10-rc1/source/arch/x86/events/intel/core.c#L2256 > There are subtle differences between Intel and AMD pmu implementation. > __intel_pmu_enable_all() enables all event with single WRMSR whereas > amd_pmu_enable_all() loops over each PMC and enables it individually. > > The WARN_ON_ONCE() is important because it will warn about potential > sw bug somewhere else. We could add a similar WARN_ON_ONCE() to the proposed patch. Thanks, George > > Thanks, > Ravi