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From: Vamsi Krishna Attunuru <vattunuru@marvell.com>
To: Greg KH <gregkh@linuxfoundation.org>
CC: Jerin Jacob <jerinj@marvell.com>, Srujana Challa <schalla@marvell.com>,
        "arnd@arndb.de" <arnd@arndb.de>,
        "linux-kernel@vger.kernel.org"
	<linux-kernel@vger.kernel.org>
Subject: RE: [EXTERNAL] Re: [PATCH v7 1/1] misc: mrvl-cn10k-dpi: add Octeon
 CN10K DPI administrative driver
Thread-Topic: [EXTERNAL] Re: [PATCH v7 1/1] misc: mrvl-cn10k-dpi: add Octeon
 CN10K DPI administrative driver
Thread-Index: AQHaqqXUeJduCBvv+0e3+QVunpJsgbG32TAAgAAF9zA=
Date: Tue, 4 Jun 2024 16:21:07 +0000
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References: <2024042950-refurbish-duckbill-77b4@gregkh>
 <20240520110630.2568767-1-vattunuru@marvell.com>
 <2024060412-amulet-unflawed-f37a@gregkh>
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> -----Original Message-----
> From: Greg KH <gregkh@linuxfoundation.org>
> Sent: Tuesday, June 4, 2024 9:23 PM
> To: Vamsi Krishna Attunuru <vattunuru@marvell.com>
> Cc: Jerin Jacob <jerinj@marvell.com>; Srujana Challa <schalla@marvell.com=
>;
> arnd@arndb.de; linux-kernel@vger.kernel.org
> Subject: [EXTERNAL] Re: [PATCH v7 1/1] misc: mrvl-cn10k-dpi: add Octeon
> CN10K DPI administrative driver
>=20
> Prioritize security for external emails: Confirm sender and content safet=
y
> before clicking links or opening attachments
>=20
> ----------------------------------------------------------------------
> On Mon, May 20, 2024 at 04:06:30AM -0700, Vamsi Attunuru wrote:
> > +union dpi_mbox_message {
> > +	u64 word[2];
> > +	struct {
> > +#if defined(__BIG_ENDIAN_BITFIELD)
> > +		/* SSO PF function */
> > +		u64 sso_pf_func  :16;
> > +		/* Aura of the command buffer */
> > +		u64 aura         :20;
> > +		/* Command buffer size in 8-byte words */
> > +		u64 csize        :16;
> > +		/* Command code */
> > +		u64 cmd          :4;
> > +		/* VF ID to configure */
> > +		u64 vfid         :8;
> > +		/* Reserved for future use */
> > +		u64 rsvd_85_127  :40;
> > +		/* Work queue completion status byte offset */
> > +		u64 wqecsoff     :7;
> > +		/* Work queue completion status enable */
> > +		u64 wqecs        :1;
> > +		/* NPA PF function */
> > +		u64 npa_pf_func  :16;
> > +#else
> > +		/* VF ID to configure */
> > +		u64 vfid         :8;
> > +		/* Command code */
> > +		u64 cmd          :4;
> > +		/* Command buffer size in 8-byte words */
> > +		u64 csize        :16;
> > +		/* Aura of the command buffer */
> > +		u64 aura         :20;
> > +		/* SSO PF function */
> > +		u64 sso_pf_func  :16;
> > +		/* NPA PF function */
> > +		u64 npa_pf_func  :16;
> > +		/* Work queue completion status enable */
> > +		u64 wqecs        :1;
> > +		/* Work queue completion status byte offset */
> > +		u64 wqecsoff     :7;
> > +		/* Reserved for future use */
> > +		u64 rsvd_85_127  :40;
> > +#endif
> > +	};
> > +};
>=20
> The ifdef is cute, but not correct, sorry.  Please use bit shifts to hand=
le this
> properly without any #ifdef needed at all.
>=20
Ack, will fix it next version. Thanks for the suggestion.

>=20
>=20
>=20
> > +
> > +static inline void dpi_reg_write(struct dpipf *dpi, u64 offset, u64
> > +val) {
> > +	writeq(val, dpi->reg_base + offset);
>=20
> No read needed after a write to ensure the write made it to the hardware
> properly?

Yes, as it's an onboard PCIe device, writes will happen properly. I will mo=
dify it as write followed by
a write barrier to avoid any reordering.

Thanks
Vamsi
>=20
> thanks,
>=20
> greg k-h