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From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Date: Tue, 4 Jun 2024 18:29:24 +0100
Message-ID: <CA+V-a8tDYjEmuZVoBk+gv-XCneEchiS91J15p8p96aKFRbo8DQ@mail.gmail.com>
Subject: Re: [PATCH v4 2/2] irqchip/renesas-rzg2l: Add support for RZ/Five SoC
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>, Rob Herring <robh@kernel.org>, 
	Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, 
	Magnus Damm <magnus.damm@gmail.com>, linux-kernel@vger.kernel.org, 
	devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, 
	Biju Das <biju.das.jz@bp.renesas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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Hi Thomas,

Thank you for the review.

On Mon, Jun 3, 2024 at 1:40=E2=80=AFPM Thomas Gleixner <tglx@linutronix.de>=
 wrote:
>
> On Tue, Apr 30 2024 at 15:14, Prabhakar wrote:
> > +
> > +static void rzfive_irqc_irq_disable(struct irq_data *d)
> > +{
> > +     rzfive_tint_irq_endisable(d, false);
> > +     irq_chip_disable_parent(d);
> > +}
> > +
> > +static void rzfive_irqc_irq_enable(struct irq_data *d)
> > +{
> > +     rzfive_tint_irq_endisable(d, true);
> > +     irq_chip_enable_parent(d);
> > +}
>
> This looks wrong. Enable/disable should be symmetric vs. ordering, no?
>
Agreed, I will reverse the order in the disable callback and send a new ver=
sion.

Cheers,
Prabhakar