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AJvYcCVffQZehLzTpr1UZyn3u32GwFzYP86ItA2H7y/ljX6BRbjiMmJjCj0lw30ysUbPL3IC+7FH9DBnr8PLMdQoYs8p2BKm3DaiHdFNuD7T0Rx9qmQdXjngCLk8bgX6CGybcLKgGQjG2Q4KvSHYy3LZ X-Gm-Message-State: AOJu0YwRQuWyChcfQXQKQ5024ZvRQRmhPZE7Tei8rzWxmzOdvT9U5hHa tdrzL7u/maAxCpDfuhmDXup67vG0x+IWOGTdwRf6GA/oS1PKoqWY X-Received: by 2002:a05:600c:154a:b0:421:2b3e:3a22 with SMTP id 5b1f17b1804b1-421562cce3dmr2749115e9.14.1717522635105; Tue, 04 Jun 2024 10:37:15 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2500:a01:2595:4364:d152:dff3]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4213c6629bdsm87844085e9.8.2024.06.04.10.37.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jun 2024 10:37:14 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v5 0/2] Add IAX45 support for RZ/Five SoC Date: Tue, 4 Jun 2024 18:37:08 +0100 Message-Id: <20240604173710.534132-1-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Lad Prabhakar Hi All, The IAX45 block on RZ/Five SoC is almost identical to the IRQC bock found on the RZ/G2L family of SoCs. IAX45 performs various interrupt controls including synchronization for the external interrupts of NMI, IRQ, and GPIOINT and the interrupts of the built-in peripheral interrupts output by each module. And it notifies the interrupt to the PLIC. - Select 32 TINT from 82 GPIOINT. - Integration of bus error interrupts from system bus. - Integration of ECC error interrupts from On-chip RAM. - Indicate interrupt status. (NMI, IRQ, TINT, integrated bus error interrupt and integrated ECC error interrupt) - Setting of interrupt detection method. (NMI, IRQ and TINT) - All interrupts are masked by INTMASK. - Mask function for NMI, IRQ and TINT This patch series adds support for IAX45 in the IRQC driver and enables this on RZ/Five SoC. v4->v5 - Reversed the operation in rzfive_irqc_irq_disable(). v3->v4 - Renamed rzg2l_irqc_init_helper -> rzg2l_irqc_common_init - Moved the locks into callers for (un)mask and (en/dis)able functions - Collected RB tag from Geert for patch#2 v2->v3 - DTS/I patches dropped from the series as they have been merged into renesas-soc tree - Just using a const from compat string instead of having it in a items - Added RZ/Five specific irqchip v2: https://patchwork.kernel.org/project/linux-renesas-soc/cover/20240403203503.634465-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ v1: https://patchwork.kernel.org/project/linux-renesas-soc/cover/20240129151618.90922-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ Cheers, Prabhakar Lad Prabhakar (2): dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/Five SoC irqchip/renesas-rzg2l: Add support for RZ/Five SoC .../renesas,rzg2l-irqc.yaml | 17 +- drivers/irqchip/irq-renesas-rzg2l.c | 148 +++++++++++++++++- 2 files changed, 155 insertions(+), 10 deletions(-) -- 2.34.1