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AJvYcCV4aMZeoc5uIkSBfChf5obwAC2GCwTg868ePKWT3Nl4XruoOYWEs0xxFMft2szl4fBq6ZcKYcjdtZMflxtZ5JrBbDTfBpPHVsp8DWbB4dTi+A4TcsA+cywiLvaAwe/7T2X1gyxBBa1eVaVl9VHv X-Gm-Message-State: AOJu0YxJ7xiiAjS2nnV5C3nnCMgBwFcYQ89ChSDy8pA8lqTFAoUkPQ+5 dj2Ynbldcwak6N/dKCx4I8vwZML8GQWNPlqsF2TXII4N3XcgTA1O X-Received: by 2002:a05:600c:19c6:b0:421:1717:2cf0 with SMTP id 5b1f17b1804b1-421562df8e7mr3129345e9.24.1717522636317; Tue, 04 Jun 2024 10:37:16 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2500:a01:2595:4364:d152:dff3]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4213c6629bdsm87844085e9.8.2024.06.04.10.37.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jun 2024 10:37:15 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar , Krzysztof Kozlowski Subject: [PATCH v5 1/2] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/Five SoC Date: Tue, 4 Jun 2024 18:37:09 +0100 Message-Id: <20240604173710.534132-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240604173710.534132-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240604173710.534132-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Lad Prabhakar Document RZ/Five (R9A07G043F) IRQC bindings. The IRQC block on the RZ/Five SoC is almost identical to the one found on the RZ/G2L SoC, with the only difference being that it has additional mask control registers for NMI/IRQ/TINT. Hence new compatible string "renesas,r9a07g043f-irqc" is added for RZ/Five SoC. Signed-off-by: Lad Prabhakar Acked-by: Krzysztof Kozlowski Reviewed-by: Geert Uytterhoeven --- v4->v5 - No change v3->v4 - No change v2->v3 - Dropped items for rz/five - Collected the RB tags v1->v2 - Dropped the checks for interrupts as its already handled - Added SoC specific compat string --- .../renesas,rzg2l-irqc.yaml | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml index daef4ee06f4e..44b6ae5fc802 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml @@ -21,13 +21,16 @@ description: | properties: compatible: - items: - - enum: - - renesas,r9a07g043u-irqc # RZ/G2UL - - renesas,r9a07g044-irqc # RZ/G2{L,LC} - - renesas,r9a07g054-irqc # RZ/V2L - - renesas,r9a08g045-irqc # RZ/G3S - - const: renesas,rzg2l-irqc + oneOf: + - items: + - enum: + - renesas,r9a07g043u-irqc # RZ/G2UL + - renesas,r9a07g044-irqc # RZ/G2{L,LC} + - renesas,r9a07g054-irqc # RZ/V2L + - renesas,r9a08g045-irqc # RZ/G3S + - const: renesas,rzg2l-irqc + + - const: renesas,r9a07g043f-irqc # RZ/Five '#interrupt-cells': description: The first cell should contain a macro RZG2L_{NMI,IRQX} included in the -- 2.34.1