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From: Rob Clark <robdclark@gmail.com>
Date: Tue, 4 Jun 2024 11:49:13 -0700
Message-ID: <CAF6AEGsxKwzX6it4vipggOdGqNVzPbwMj6a0h871a=GfwUp0Cg@mail.gmail.com>
Subject: Re: [PATCH v9 3/5] iommu/arm-smmu: introduction of ACTLR for custom
 prefetcher settings
To: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>, Konrad Dybcio <konrad.dybcio@linaro.org>, 
	will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, jsnitsel@redhat.com, 
	quic_bjorande@quicinc.com, mani@kernel.org, quic_eberman@quicinc.com, 
	robdclark@chromium.org, u.kleine-koenig@pengutronix.de, robh@kernel.org, 
	vladimir.oltean@nxp.com, quic_pkondeti@quicinc.com, quic_molvera@quicinc.com, 
	linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, 
	iommu@lists.linux.dev, linux-kernel@vger.kernel.org
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On Thu, May 30, 2024 at 2:22=E2=80=AFAM Bibek Kumar Patro
<quic_bibekkum@quicinc.com> wrote:
>
>
>
> On 5/28/2024 9:38 PM, Rob Clark wrote:
> > On Tue, May 28, 2024 at 6:06=E2=80=AFAM Dmitry Baryshkov
> > <dmitry.baryshkov@linaro.org> wrote:
> >>
> >> On Tue, May 28, 2024 at 02:59:51PM +0200, Konrad Dybcio wrote:
> >>>
> >>>
> >>> On 5/15/24 15:59, Bibek Kumar Patro wrote:
> >>>>
> >>>>
> >>>> On 5/10/2024 6:32 PM, Konrad Dybcio wrote:
> >>>>> On 10.05.2024 2:52 PM, Bibek Kumar Patro wrote:
> >>>>>>
> >>>>>>
> >>>>>> On 5/1/2024 12:30 AM, Rob Clark wrote:
> >>>>>>> On Tue, Jan 23, 2024 at 7:00=E2=80=AFAM Bibek Kumar Patro
> >>>>>>> <quic_bibekkum@quicinc.com> wrote:
> >>>>>>>>
> >>>>>>>> Currently in Qualcomm  SoCs the default prefetch is set to 1 whi=
ch allows
> >>>>>>>> the TLB to fetch just the next page table. MMU-500 features ACTL=
R
> >>>>>>>> register which is implementation defined and is used for Qualcom=
m SoCs
> >>>>>>>> to have a custom prefetch setting enabling TLB to prefetch the n=
ext set
> >>>>>>>> of page tables accordingly allowing for faster translations.
> >>>>>>>>
> >>>>>>>> ACTLR value is unique for each SMR (Stream matching register) an=
d stored
> >>>>>>>> in a pre-populated table. This value is set to the register duri=
ng
> >>>>>>>> context bank initialisation.
> >>>>>>>>
> >>>>>>>> Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
> >>>>>>>> ---
> >>>>>
> >>>>> [...]
> >>>>>
> >>>>>>>> +
> >>>>>>>> +               for_each_cfg_sme(cfg, fwspec, j, idx) {
> >>>>>>>> +                       smr =3D &smmu->smrs[idx];
> >>>>>>>> +                       if (smr_is_subset(smr, id, mask)) {
> >>>>>>>> +                               arm_smmu_cb_write(smmu, cbndx, A=
RM_SMMU_CB_ACTLR,
> >>>>>>>> +                                               actlrcfg[i].actl=
r);
> >>>>>>>
> >>>>>>> So, this makes ACTLR look like kind of a FIFO.  But I'm looking a=
t
> >>>>>>> downstream kgsl's PRR thing (which we'll need to implement vulkan
> >>>>>>> sparse residency), and it appears to be wanting to set BIT(5) in =
ACTLR
> >>>>>>> to enable PRR.
> >>>>>>>
> >>>>>>>            val =3D KGSL_IOMMU_GET_CTX_REG(ctx, KGSL_IOMMU_CTX_ACT=
LR);
> >>>>>>>            val |=3D FIELD_PREP(KGSL_IOMMU_ACTLR_PRR_ENABLE, 1);
> >>>>>>>            KGSL_IOMMU_SET_CTX_REG(ctx, KGSL_IOMMU_CTX_ACTLR, val)=
;
> >>>>>>>
> >>>>>>> Any idea how this works?  And does it need to be done before or a=
fter
> >>>>>>> the ACTLR programming done in this patch?
> >>>>>>>
> >>>>>>> BR,
> >>>>>>> -R
> >>>>>>>
> >>>>>>
> >>>>>> Hi Rob,
> >>>>>>
> >>>>>> Can you please help provide some more clarification on the FIFO pa=
rt? By FIFO are you referring to the storing of ACTLR data in the table?
> >>>>>>
> >>>>>> Thanks for pointing to the downstream implementation of kgsl drive=
r for
> >>>>>> the PRR bit. Since kgsl driver is already handling this PRR bit's
> >>>>>> setting, this makes setting the PRR BIT(5) by SMMU driver redundan=
t.
> >>>>>
> >>>>> The kgsl driver is not present upstream.
> >>>>>
> >>>>
> >>>> Right kgsl is not present upstream, it would be better to avoid conf=
iguring the PRR bit and can be handled by kgsl directly in downstream.
> >>>
> >>> No! Upstream is not a dumping ground to reduce your technical debt.
> >>>
> >>> There is no kgsl driver upstream, so this ought to be handled here, i=
n
> >>> the iommu driver (as poking at hardware A from driver B is usually no=
t good
> >>> practice).
> >>
> >> I'd second the request here. If another driver has to control the
> >> behaviour of another driver, please add corresponding API for that.
> >
> > We have adreno_smmu_priv for this purpose ;-)
> >
>
> Thanks Rob for pointing to this private interface structure between smmu
> and gpu. I think it's similar to what you're trying to implement here
> https://lore.kernel.org/all/CAF6AEGtm-KweFdMFvahH1pWmpOq7dW_p0Xe_13aHGWt0=
jSbg8w@mail.gmail.com/#t
> I can add an api "set_actlr_prr()" with smmu_domain cookie, page pointer
> as two parameters. This api then can be used by drm/msm driver to carry
> out the prr implementation by simply calling this.
> Would this be okay Rob,Konrad,Dmitry?
> Let me know if any other suggestions you have in mind as well regarding
> parameters and placement.

Hey Bibek, quick question.. is ACTLR preserved across a suspend/resume
cycle?  Or does it need to be reprogrammed on resume?  And same
question for these two PRR related regs:

  /* Global SMMU register offsets */
  #define KGSL_IOMMU_PRR_CFG_LADDR        0x6008
  #define KGSL_IOMMU_PRR_CFG_UADDR        0x600c

(ie. high/low 32b of the PRR page)

I was starting to type up a patch to add PRR configuration, but
depending on whether it interacts with suspend/resume, it might be
better form arm-smmu-qcom.c to just always enable and configure PRR
(including allocating a page to have an address to program into
PRR_CFG_LADDR/UADDR), and instead add an interface to return the PRR
page?  I think there is no harm in unconditionally configuring PRR for
gpu smmu.

BR,
-R

> Thanks & regards,
> Bibek
>
> > BR,
> > -R
> >
> >>>
> >>>>
> >>>>>> Thanks for bringing up this point.
> >>>>>> I will send v10 patch series removing this BIT(5) setting from the=
 ACTLR
> >>>>>> table.
> >>>>>
> >>>>> I think it's generally saner to configure the SMMU from the SMMU dr=
iver..
> >>>>
> >>>> Yes, agree on this. But since PRR bit is not directly related to SMM=
U
> >>>> configuration so I think it would be better to remove this PRR bit
> >>>> setting from SMMU driver based on my understanding.
> >>>
> >>> Why is it not related? We still don't know what it does.
> >>>
> >>> Konrad
> >>
> >> --
> >> With best wishes
> >> Dmitry