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Date: Wed, 5 Jun 2024 09:12:48 +0200
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Subject: Re: [PATCH] arm64: dts: st: OP-TEE async notif on PPI 15 for
 stm32mp25
To: Pascal Paillet <p.paillet@foss.st.com>, Rob Herring <robh@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley
	<conor+dt@kernel.org>,
        Maxime Coquelin <mcoquelin.stm32@gmail.com>,
        <devicetree@vger.kernel.org>,
        <linux-stm32@st-md-mailman.stormreply.com>,
        <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>
References: <20240521080131.473447-1-p.paillet@foss.st.com>
Content-Language: en-US
From: Alexandre TORGUE <alexandre.torgue@foss.st.com>
In-Reply-To: <20240521080131.473447-1-p.paillet@foss.st.com>
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Hi

On 5/21/24 10:01, Pascal Paillet wrote:
> From: Etienne Carriere <etienne.carriere@foss.st.com>
> 
> Define GIC PPI 15 (aka GIC interrupt line 31) for OP-TEE asynchronous
> notification.
> 
> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
> Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
> ---
>   arch/arm64/boot/dts/st/stm32mp251.dtsi | 4 +++-
>   arch/arm64/boot/dts/st/stm32mp253.dtsi | 4 ++++
>   2 files changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi
> index 4b48e4ed2d28..d0e10dda96b6 100644
> --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi
> +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi
> @@ -51,9 +51,11 @@ clk_rcbsec: clk-rcbsec {
>   	};
>   
>   	firmware {
> -		optee {
> +		optee: optee {
>   			compatible = "linaro,optee-tz";
>   			method = "smc";
> +			interrupt-parent = <&intc>;
> +			interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
>   		};
>   
>   		scmi {
> diff --git a/arch/arm64/boot/dts/st/stm32mp253.dtsi b/arch/arm64/boot/dts/st/stm32mp253.dtsi
> index 029f88981961..69001f924d17 100644
> --- a/arch/arm64/boot/dts/st/stm32mp253.dtsi
> +++ b/arch/arm64/boot/dts/st/stm32mp253.dtsi
> @@ -28,3 +28,7 @@ timer {
>   			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
>   	};
>   };
> +
> +&optee {
> +	interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
> +};

Applied on stm32-next.

Thanks
Alex