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Message-ID: <8dcac591e5dc9d4cc1a6cf89512d08ef12457474.camel@gmail.com>
Subject: Re: [PATCH v2 2/3] dt-bindings: iio: adc: ad7192: Fix clock config
From: Nuno =?ISO-8859-1?Q?S=E1?= <noname.nuno@gmail.com>
To: Alisa-Dariana Roman <alisadariana@gmail.com>, Alisa-Dariana Roman
 <alisa.roman@analog.com>, Jonathan Cameron <Jonathan.Cameron@huawei.com>, 
 Michael Hennerich <michael.hennerich@analog.com>,
 linux-iio@vger.kernel.org, devicetree@vger.kernel.org, 
 linux-kernel@vger.kernel.org
Cc: Lars-Peter Clausen <lars@metafoo.de>, Alexandru Tachici
 <alexandru.tachici@analog.com>, Jonathan Cameron <jic23@kernel.org>, Rob
 Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor
 Dooley <conor+dt@kernel.org>, Liam Girdwood <lgirdwood@gmail.com>, Mark
 Brown <broonie@kernel.org>
Date: Wed, 05 Jun 2024 10:26:20 +0200
In-Reply-To: <20240605075154.625123-2-alisa.roman@analog.com>
References: <20240605075154.625123-1-alisa.roman@analog.com>
	 <20240605075154.625123-2-alisa.roman@analog.com>
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On Wed, 2024-06-05 at 10:51 +0300, Alisa-Dariana Roman wrote:
> There are actually 4 configuration modes of clock source for AD719X
> devices. Either a crystal can be attached externally between MCLK1 and
> MCLK2 pins, or an external CMOS-compatible clock can drive the MCLK2
> pin. The other 2 modes make use of the 4.92MHz internal clock, which can
> be made available on the MCLK2 pin.
>=20
> The presence of an external clock is optional, not required.
>=20
> Fixes: f7356e47032c ("dt-bindings: iio: adc: ad7192: Add binding document=
ation
> for AD7192")
> Signed-off-by: Alisa-Dariana Roman <alisa.roman@analog.com>
> ---
> =C2=A0.../bindings/iio/adc/adi,ad7192.yaml=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0 | 19 ++++++++++---------
> =C2=A01 file changed, 10 insertions(+), 9 deletions(-)
>=20
> diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml
> b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml
> index a03da9489ed9..c5a4219a9388 100644
> --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml
> +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml
> @@ -39,11 +39,16 @@ properties:
> =C2=A0
> =C2=A0=C2=A0 clocks:
> =C2=A0=C2=A0=C2=A0=C2=A0 maxItems: 1
> -=C2=A0=C2=A0=C2=A0 description: phandle to the master clock (mclk)
> +=C2=A0=C2=A0=C2=A0 description: |
> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 Optionally, either a crystal can be attac=
hed externally between MCLK1
> and
> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 MCLK2 pins, or an external CMOS-compatibl=
e clock can drive the MCLK2
> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 pin. If absent, internal 4.92MHz clock is=
 used which can be made
> available
> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 on MCLK2.
> =C2=A0
> =C2=A0=C2=A0 clock-names:
> -=C2=A0=C2=A0=C2=A0 items:
> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - const: mclk
> +=C2=A0=C2=A0=C2=A0 enum:
> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - xtal
> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - clk

Not sure about changing the name of the clock... Isn't this breaking ABI?

- Nuno S=C3=A1