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Message-ID: <e1c29dd4-2eb9-44fe-abf2-f5ca0e84e2a6@amd.com>
Date: Wed, 5 Jun 2024 17:08:01 +0530
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From: Ravi Bangoria <ravi.bangoria@amd.com>
Subject: Re: [PATCH 3/3] KVM SVM: Add Bus Lock Detect support
To: Sean Christopherson <seanjc@google.com>
Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de,
 dave.hansen@linux.intel.com, pbonzini@redhat.com, thomas.lendacky@amd.com,
 hpa@zytor.com, rmk+kernel@armlinux.org.uk, peterz@infradead.org,
 james.morse@arm.com, lukas.bulwahn@gmail.com, arjan@linux.intel.com,
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 michael.roth@amd.com, nikunj.dadhania@amd.com, babu.moger@amd.com,
 x86@kernel.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
 santosh.shukla@amd.com, ananth.narayan@amd.com, sandipan.das@amd.com,
 ravi.bangoria@amd.com
References: <20240429060643.211-1-ravi.bangoria@amd.com>
 <20240429060643.211-4-ravi.bangoria@amd.com> <Zl5jqwWO4FyawPHG@google.com>
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Hi Sean,

On 6/4/2024 6:15 AM, Sean Christopherson wrote:
> On Mon, Apr 29, 2024, Ravi Bangoria wrote:
>> Upcoming AMD uarch will support Bus Lock Detect. Add support for it
>> in KVM. Bus Lock Detect is enabled through MSR_IA32_DEBUGCTLMSR and
>> MSR_IA32_DEBUGCTLMSR is virtualized only if LBR Virtualization is
>> enabled. Add this dependency in the KVM.
> 
> This is woefully incomplete, e.g. db_interception() needs to be updated to decipher
> whether the #DB is the responsbility of the host or of the guest.

Can you please elaborate. Are you referring to vcpu->guest_debug thingy?

> Honestly, I don't see any point in virtualizing this in KVM.  As Jim alluded to,
> what's far, far more interesting for KVM is "Bus Lock Threshold".  Virtualizing
> this for the guest would have been nice to have during the initial split-lock #AC
> support, but now I'm skeptical the complexity is worth the payoff.

This has a valid usecase of penalizing offending processes. I'm not sure
how much it's really used in the production though.

> I suppose we could allow it if #DB isn't interecepted, at which point the enabling
> required is minimal?

The feature uses DEBUG_CTL MSR, #DB and DR6 register. Do you mean expose
it when all three are accelerated or just #DB?

Thanks for the feedback,
Ravi