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[209.85.219.182]) by smtp.gmail.com with ESMTPSA id 00721157ae682-62c766afffcsm21823707b3.108.2024.06.05.04.41.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 05 Jun 2024 04:41:44 -0700 (PDT) Received: by mail-yb1-f182.google.com with SMTP id 3f1490d57ef6-df771b45e13so2219655276.2; Wed, 05 Jun 2024 04:41:44 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCWoDYmsVGzfDZxbGpHb0eRmxCxMYRvReu6Vfvmyi8GDq1T7zvOVp+j2WNejprlvxTtSVZxvILRXZUA/8jomB1OnUIbQ61xE++VglI8LV/Rj38zw7OwzXatFqVFwpp3MfkuPK5tMBtDcDGtQ2pCQD/rdVBgpXk886T9iE7Xo6z7UPvoBR0bMKHVaZowAuUb+1RUV9A5Ch4nBJPbgPsszxpGCKRaCXK1Z9g== X-Received: by 2002:a05:6902:4ce:b0:dfa:b47b:e9fb with SMTP id 3f1490d57ef6-dfacaceda90mr2104197276.52.1717587703941; Wed, 05 Jun 2024 04:41:43 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240530173857.164073-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20240530173857.164073-4-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20240530173857.164073-4-prabhakar.mahadev-lad.rj@bp.renesas.com> From: Geert Uytterhoeven Date: Wed, 5 Jun 2024 13:41:31 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v3 03/15] pinctrl: renesas: pinctrl-rzg2l: Allow more bits for pin configuration To: Prabhakar Cc: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Biju Das , Claudiu Beznea , Fabrizio Castro , Paul Barker , Lad Prabhakar Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, May 30, 2024 at 7:41=E2=80=AFPM Prabhakar wrote: > From: Lad Prabhakar > > The pin configuration bits have been growing for every new SoCs being > added for the pinctrl-rzg2l driver which would mean updating the macros > every time for each new configuration. To avoid this allocate additional > bits for pin configuration by relocating the known fixed bits to the very > end of the configuration. > > Also update the size of 'cfg' to 'u64' to allow more configuration bits i= n > the 'struct rzg2l_variable_pin_cfg'. > > Signed-off-by: Lad Prabhakar > --- > v2->v3 > - Updated size for cfg in struct rzg2l_variable_pin_cfg Reviewed-by: Geert Uytterhoeven Gr{oetje,eeting}s, Geert --=20 Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k= .org In personal conversations with technical people, I call myself a hacker. Bu= t when I'm talking to journalists I just say "programmer" or something like t= hat. -- Linus Torvalds