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Date: Wed, 5 Jun 2024 16:45:03 +0100
From: Conor Dooley <conor@kernel.org>
To: Jesse Taube <jesse@rivosinc.com>
Cc: linux-riscv@lists.infradead.org,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Conor Dooley <conor.dooley@microchip.com>,
	Evan Green <evan@rivosinc.com>,
	Charlie Jenkins <charlie@rivosinc.com>,
	Andrew Jones <ajones@ventanamicro.com>,
	=?iso-8859-1?Q?Cl=E9ment_L=E9ger?= <cleger@rivosinc.com>,
	Xiao Wang <xiao.w.wang@intel.com>, Andy Chiu <andy.chiu@sifive.com>,
	Costa Shulyupin <costa.shul@redhat.com>,
	=?iso-8859-1?Q?Bj=F6rn_T=F6pel?= <bjorn@rivosinc.com>,
	Ben Dooks <ben.dooks@codethink.co.uk>,
	"Gustavo A. R. Silva" <gustavoars@kernel.org>,
	Alexandre Ghiti <alexghiti@rivosinc.com>,
	Erick Archer <erick.archer@gmx.com>, linux-kernel@vger.kernel.org
Subject: Re: [RFC PATCH v0] RISCV: Report vector unaligned accesses hwprobe
Message-ID: <20240605-chowtime-mannish-d0f428acd173@spud>
References: <20240604162457.3757417-1-jesse@rivosinc.com>
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On Tue, Jun 04, 2024 at 12:42:10PM -0400, Jesse Taube wrote:
> On 6/4/24 12:24, Jesse Taube wrote:
> > diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/ke=
rnel/unaligned_access_speed.c
> > index a9a6bcb02acf..92a84239beaa 100644
> > --- a/arch/riscv/kernel/unaligned_access_speed.c
> > +++ b/arch/riscv/kernel/unaligned_access_speed.c
> > @@ -20,6 +20,7 @@
> >   #define MISALIGNED_COPY_SIZE ((MISALIGNED_BUFFER_SIZE / 2) - 0x80)
> >   DEFINE_PER_CPU(long, misaligned_access_speed);
> > +DEFINE_PER_CPU(long, vector_misaligned_access) =3D RISCV_HWPROBE_VEC_M=
ISALIGNED_UNKNOWN;
> >   #ifdef CONFIG_RISCV_PROBE_UNALIGNED_ACCESS
> >   static cpumask_t fast_misaligned_access;
> > @@ -264,6 +265,8 @@ static int check_unaligned_access_all_cpus(void)
> >   {
> >   	bool all_cpus_emulated =3D check_unaligned_access_emulated_all_cpus(=
);
>=20
> There was talks about Zicclsm, but spike doesnt have support for Zicclsm
> afaik,

Support for Zicclsm just means that it can perform misaligned loads and
stores to cache coherent memory. I guess support in Spike would involve
setting that in its devicetree iff/when that's the case.

> but I was wondering if i should add Zicclsm to cpufeature and aswell.

Ye, please do add detection for Zicclsm. I think that should be fairly
straightforward to do, nothing too special to document.

Cheers,
Conor.

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