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AJvYcCUow1ABjnyHTRT3uKQgSlL+umGS9tFImDXCoWYU00InfLgnTtbPMW8TuoPptv/UKPuxSvUpHn/hgS0I0i6IVaBQV4Fll5+OZamr0zEZHdLkcs8Td1NQ2D6HI77M3uTwCNSjckucwxC9HIImK76jjwZQgesi0gu7OtuEPxs14OEBokMxOw== X-Gm-Message-State: AOJu0YxIZG82hWwsySvi6fPBZQpReNN0WkaEcd2TqN8MlURNSq4P7+1j pi296hkwm+ul18EwZ68gi8Se6G6WYD6vl1qYZ8vIgXvduMv/4MY= X-Received: by 2002:a5d:6d8f:0:b0:34c:7ed4:55a with SMTP id ffacd0b85a97d-35ef0ddb092mr806043f8f.33.1717621252274; Wed, 05 Jun 2024 14:00:52 -0700 (PDT) Received: from U4.lan ([2a02:810b:f40:4600:5211:58fe:dfef:c48c]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-35dd04c0d77sm15955721f8f.5.2024.06.05.14.00.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 14:00:52 -0700 (PDT) From: Alex Bee To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Michael Turquette , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Alex Bee Subject: [PATCH v2 2/5 RESEND] dt-bindings: clock: rk3128: Drop CLK_NR_CLKS Date: Wed, 5 Jun 2024 23:00:46 +0200 Message-ID: <20240605210049.232284-3-knaerzche@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240605210049.232284-1-knaerzche@gmail.com> References: <20240605210049.232284-1-knaerzche@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit CLK_NR_CLKS should not be part of the binding. Let's drop it, since the kernel code no longer uses it either. Signed-off-by: Alex Bee --- changes since v1: - new patch include/dt-bindings/clock/rk3128-cru.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/dt-bindings/clock/rk3128-cru.h b/include/dt-bindings/clock/rk3128-cru.h index 1be455ba4985..420984fc2285 100644 --- a/include/dt-bindings/clock/rk3128-cru.h +++ b/include/dt-bindings/clock/rk3128-cru.h @@ -145,7 +145,6 @@ #define HCLK_CRYPTO 476 #define HCLK_PERI 478 -#define CLK_NR_CLKS (HCLK_PERI + 1) /* soft-reset indices */ #define SRST_CORE0_PO 0 -- 2.45.2