Received: by 2002:ab2:6309:0:b0:1fb:d597:ff75 with SMTP id s9csp44481lqt; Wed, 5 Jun 2024 16:43:43 -0700 (PDT) X-Forwarded-Encrypted: i=3; AJvYcCWxKJTcpgqYelOmGGy9jn9JlWrGtZRRfE26FY1oNVH/BqDrWrqbabtiXTiK7ddZq/e9GH202jj2RkzzoGtgFrwbWUJkpvSkPxHxkfE0Dg== X-Google-Smtp-Source: AGHT+IFB84ZXCMKYecl9/kCKfOjqSUQF/v/nkrxq/hD9chGQyL5TBZgqwtqaDc7TmFqcjsz2PDZg X-Received: by 2002:a50:d752:0:b0:578:5f53:f017 with SMTP id 4fb4d7f45d1cf-57aa5405bc0mr842065a12.6.1717631023304; Wed, 05 Jun 2024 16:43:43 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1717631023; cv=pass; d=google.com; s=arc-20160816; b=QEM05jJDxnVqQsLxzhSJJ/dJoug2Ssa6Vb+shulCWHLwsuaP5WzOPhwzgk1EgLIi/s 8Kxcy6U9qbRsUiw6LOpBl00yqQgAYb3CdIOPPI74lpL0WcqpFfIxzmH8bwk6n6BN8u17 6JEMRIX4hOMGsTT+F1Be2SoOhNY29tOPE1xN0vi9X4sVwjHcqdjTW7rUBFaw3Hzd0Xig Ob+h7NFimTXzhDHmBboBCY5GbkoGIGYBLYg10diVJydiPfuP/cCqktoxiPm/oMH0M2py Nw2yH+ExdJoAhDBkghFZGF9Aks3vhoY4PQ8U21GdOeBY47CLd/ELJpJbHvKLl4TVwBjH 8tiA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=in-reply-to:content-disposition:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:message-id:subject:cc :to:from:date:dkim-signature; bh=u2cpct7+XFJzG7wX3keUvQVf0CUO4FB1mefATz3+4Jw=; fh=FC9+jri0/UuNvEscR48G+Xjjy9/QT+UDDaLLHMtH8U8=; b=VFInzrGLaDTWrVabc2PF9XViqXBoQMFJHtpb53xQyxbPGsOupVooHnjbsVBXigIwSe XA5IJjAtzfdSILRKuibDjDMEL/HG9osrJsAbZS/V1npZw5CKYmMNRKFS1RR0tqVWhRvs 4RAbF/E2rNmABDcK4zv7d964leEPSEBksIrez12f5uITmTDWAhRGzObMe87NwXKxMWSA O3lok8yAdTfTvB8dLScdzBiYmGlVUIgOb04kn7GMV02QiphuzPy8j6FOXy4+VH/Jrto0 Ge/ho+C2Db9Ss2rKlGlAQNx23/7GutLH60QgieXXoHcj6uxYKnqYRLyTL1crzbvSleW1 BxXg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@lunn.ch header.s=20171124 header.b=NAPHVF8w; arc=pass (i=1 spf=pass spfdomain=lunn.ch dkim=pass dkdomain=lunn.ch dmarc=pass fromdomain=lunn.ch); spf=pass (google.com: domain of linux-kernel+bounces-203415-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-203415-linux.lists.archive=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=lunn.ch Return-Path: Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. [147.75.80.249]) by mx.google.com with ESMTPS id 4fb4d7f45d1cf-57aae0c6628si66706a12.81.2024.06.05.16.43.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 16:43:43 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel+bounces-203415-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) client-ip=147.75.80.249; Authentication-Results: mx.google.com; dkim=pass header.i=@lunn.ch header.s=20171124 header.b=NAPHVF8w; arc=pass (i=1 spf=pass spfdomain=lunn.ch dkim=pass dkdomain=lunn.ch dmarc=pass fromdomain=lunn.ch); spf=pass (google.com: domain of linux-kernel+bounces-203415-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-203415-linux.lists.archive=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=lunn.ch Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by am.mirrors.kernel.org (Postfix) with ESMTPS id E2D251F20FC6 for ; Wed, 5 Jun 2024 23:43:42 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 23E8C168C2E; Wed, 5 Jun 2024 23:43:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b="NAPHVF8w" Received: from vps0.lunn.ch (vps0.lunn.ch [156.67.10.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35097167268; Wed, 5 Jun 2024 23:43:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=156.67.10.101 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717631010; cv=none; b=e4oH+JbOBEO1k1Jb46W4ikDYLxmk0EG3eB41/S54A+JAU5es7GkgKkENwhbi0rBepoRmYNnmv4Jz++VpGY3zhC4w9FNefndVAgKjAhST1gUtH0xTe1BVplXd0GGvhwfHyI2dhT/wOYQ3gJ1iAthOr/tMMzBH/jXspfJZmnaJ4Qc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717631010; c=relaxed/simple; bh=iK3LAb+wliolnG3rKsU2JLIVpkEh3hwHDV0sMObCrZQ=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=qQgxASMRsFWd6zsvYw8DXgpHhhGyH//lkGt7vgnVEq5aoqvOlSHXbN2pDxnvGo/LVOsVweRFmgkydi/4pDu+mfKKzwH8t2os0g5HDpw+gu8jhCQ2JElph/oLn14HmPiQr1pSGHMbLutwroPWzmkUJYhM+fwgqpaksxgeQyWVUgw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=lunn.ch; spf=pass smtp.mailfrom=lunn.ch; dkim=pass (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b=NAPHVF8w; arc=none smtp.client-ip=156.67.10.101 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=lunn.ch Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=lunn.ch DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Disposition:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:From:Sender:Reply-To:Subject: Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=u2cpct7+XFJzG7wX3keUvQVf0CUO4FB1mefATz3+4Jw=; b=NAPHVF8wRn7aVlrTHb60+BQh3v qp7CjSe3+zo1HV6qf8fWIjxPzGBsRU8KJzte+rHlB4+9yLfPT+Yj72wJXTItgfwJqHb9qUI8wkA6P K6WQpQwKHLlOJjJcCVvkVPJqmh6pdoSwhOrFvoOM4rY9nOlRlhR/i1yyEkx27PxdM+go=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1sF0HX-00GxVp-0T; Thu, 06 Jun 2024 01:43:03 +0200 Date: Thu, 6 Jun 2024 01:43:02 +0200 From: Andrew Lunn To: Selvamani Rajagopal Cc: "Parthiban.Veerasooran@microchip.com" , Piergiorgio Beruto , "davem@davemloft.net" , "edumazet@google.com" , "kuba@kernel.org" , "pabeni@redhat.com" , "horms@kernel.org" , "saeedm@nvidia.com" , "anthony.l.nguyen@intel.com" , "netdev@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "corbet@lwn.net" , "linux-doc@vger.kernel.org" , "robh+dt@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "conor+dt@kernel.org" , "devicetree@vger.kernel.org" , "Horatiu.Vultur@microchip.com" , "ruanjinjie@huawei.com" , "Steen.Hegelund@microchip.com" , "vladimir.oltean@nxp.com" , "UNGLinuxDriver@microchip.com" , "Thorsten.Kummermehr@microchip.com" , "Nicolas.Ferre@microchip.com" , "benjamin.bigler@bernformulastudent.ch" , Viliam Vozar , Arndt Schuebel Subject: Re: [PATCH net-next v4 00/12] Add support for OPEN Alliance 10BASE-T1x MACPHY Serial Interface Message-ID: <732ce616-9ddc-4564-ab1f-ac7bbc591292@lunn.ch> References: <6e4c8336-2783-45dd-b907-6b31cf0dae6c@lunn.ch> <0581b64a-dd7a-43d7-83f7-657ae93cefe5@lunn.ch> <39a62649-813a-426c-a2a6-4991e66de36e@microchip.com> <585d7709-bcee-4a0e-9879-612bf798ed45@lunn.ch> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Wed, Jun 05, 2024 at 09:40:12PM +0000, Selvamani Rajagopal wrote: > Parthiban/Andrew, > > Couple of requests / suggestions after completing the integration of our drivers to the current framework. Please configure your email client to wrap lines at about 78 characters. > > 1) Can we move memory map selector definitions (OA_TC6_PHY_C45_PCS_MMS2 and other 4 definitions) to the header file > include/linux/oa_tc6.h? > Also, if possible, could we add the MMS0, MMS1?. Our driver is using them. Of course, we could add it when we submit our driver. Interesting. So you have vendor registers outside of MMS 10-15? Or do you need to access standard registers? I would prefer to see your use cases before deciding this. If you want to access standard registers, you are probably doing stuff other vendors also want to do, so we should add a helper in the framework. 2) If it not too late to ask, Is it possible to move interrupt > handler to vendor's code? I would say no, not at the moment. What we can do in the future is allow a driver to register a function to handle the vendor interrupts, leaving the framework to handle the standard interrupts, and chain into the specific driver vendor interrupt handler when a vendor interrupt it indicated. > This way, it will provide vendors' code an ability to deal with some > of the interrupts. For example, our code deals with PHYINT bit. Please explain what you are doing here? What are you doing which the framework does not cover. Andrew