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[2604:1380:45e3:2400::1]) by mx.google.com with ESMTPS id 41be03b00d2f7-6de28959d07si444704a12.620.2024.06.05.20.58.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 20:58:27 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel+bounces-203600-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) client-ip=2604:1380:45e3:2400::1; Authentication-Results: mx.google.com; arc=pass (i=1 spf=pass spfdomain=arm.com dmarc=pass fromdomain=arm.com); spf=pass (google.com: domain of linux-kernel+bounces-203600-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-203600-linux.lists.archive=gmail.com@vger.kernel.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id 032892852E2 for ; Thu, 6 Jun 2024 03:58:27 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 09944208B6; Thu, 6 Jun 2024 03:58:20 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 28BE317579; Thu, 6 Jun 2024 03:58:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717646299; cv=none; b=CFG4tTdKwgdgeyIkw4OAev7wYn78GRIUnn5pj+ybvOxVzQCSyzHWJhtLvIjfcrbwcLqNzs4cU6VHOIkFvFiCAsETp0NJE58kcLyf5RCpEHD7Ji+v8wzTuNfiL2+avWj+SpsZ9si1OQuSRUjii3PTnE68qtnj60oEAgx2H3Krd88= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717646299; c=relaxed/simple; bh=+phaAw/KzcXCMt/nllQsT4B1286Zl4xZ6TDEpS52VpI=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=mC7wI8twVUUMKO3p3H42+6hum3kS+TpiiFfnk1MWqyXJmlsLX+P2PAtLLpDHTxNFLpr6RfoYiiyBA8WdL9Ahll3Hw8u78Z6yM23urp0StuNoh4iBs/E0LEOat0smAAh+EHSGfOsmkQH8SFV+01xiq98YHv2NRp/xib/fFTKbYp4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5915E339; Wed, 5 Jun 2024 20:58:40 -0700 (PDT) Received: from [10.162.40.16] (a077893.blr.arm.com [10.162.40.16]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6F2E23F64C; Wed, 5 Jun 2024 20:58:11 -0700 (PDT) Message-ID: Date: Thu, 6 Jun 2024 09:27:49 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V17 0/9] arm64/perf: Enable branch stack sampling Content-Language: en-US To: James Clark , mark.rutland@arm.com Cc: Mark Brown , Rob Herring , Marc Zyngier , Suzuki Poulose , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , linux-perf-users@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, will@kernel.org, catalin.marinas@arm.com References: <20240405024639.1179064-1-anshuman.khandual@arm.com> <80d33844-bdd2-4fee-81dd-9cd37c63d42c@arm.com> From: Anshuman Khandual In-Reply-To: <80d33844-bdd2-4fee-81dd-9cd37c63d42c@arm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 5/30/24 15:17, James Clark wrote: > > > On 05/04/2024 03:46, Anshuman Khandual wrote: >> This series enables perf branch stack sampling support on arm64 platform >> via a new arch feature called Branch Record Buffer Extension (BRBE). All >> the relevant register definitions could be accessed here. >> >> https://developer.arm.com/documentation/ddi0601/2021-12/AArch64-Registers >> >> This series applies on 6.9-rc2. >> >> Also this series is being hosted below for quick access, review and test. >> >> https://git.gitlab.arm.com/linux-arm/linux-anshuman.git (brbe_v17) >> >> There are still some open questions regarding handling multiple perf events >> with different privilege branch filters getting on the same PMU, supporting >> guest branch stack tracing from the host etc. Finally also looking for some >> suggestions regarding supporting BRBE inside the guest. The series has been >> re-organized completely as suggested earlier. >> >> - Anshuman >> > [...] >> >> ------------------ Possible 'branch_sample_type' Mismatch ----------------- >> >> Branch stack sampling attributes 'event->attr.branch_sample_type' generally >> remain the same for all the events during a perf record session. >> >> $perf record -e -e -j [workload] >> >> event_1->attr.branch_sample_type == event_2->attr.branch_sample_type >> >> This 'branch_sample_type' is used to configure the BRBE hardware, when both >> events i.e and get scheduled on a given PMU. But during >> PMU HW event's privilege filter inheritance, 'branch_sample_type' does not >> remain the same for all events. Let's consider the following example >> >> $perf record -e cycles:u -e instructions:k -j any,save_type ls >> >> cycles->attr.branch_sample_type != instructions->attr.branch_sample_type >> >> Because cycles event inherits PERF_SAMPLE_BRANCH_USER and instruction event >> inherits PERF_SAMPLE_BRANCH_KERNEL. The proposed solution here configures >> BRBE hardware with 'branch_sample_type' from last event to be added in the >> PMU and hence captured branch records only get passed on to matching events >> during a PMU interrupt. >> > > Hi Anshuman, > > Surely because of this example we should merge? At least we have to try > to make the most common basic command lines work. Unless we expect all > tools to know whether the branch buffer is shared between PMUs on each > architecture or not. The driver knows though, so can merge the settings > because it all has to go into one BRBE. > > Merging the settings in tools would be a much harder problem. Alright, makes sense. > > Any user that doesn't have permission for anything in the merged result > can continue to get nothing. > > And we can always add filtering in the kernel later on if we want to to > make it appear to behave even more normally. Understood. > >> static int >> armpmu_add(struct perf_event *event, int flags) >> { >> ........ >> if (has_branch_stack(event)) { >> /* >> * Reset branch records buffer if a new task event gets >> * scheduled on a PMU which might have existing records. >> * Otherwise older branch records present in the buffer >> * might leak into the new task event. >> */ >> if (event->ctx->task && hw_events->brbe_context != event->ctx) { >> hw_events->brbe_context = event->ctx; >> if (armpmu->branch_reset) >> armpmu->branch_reset(); >> } >> hw_events->brbe_users++; >> Here -------> hw_events->brbe_sample_type = event->attr.branch_sample_type; >> } >> ........ >> } >> >> Instead of overriding existing 'branch_sample_type', both could be merged. >> > > I can't see any use case where anyone would want the override behavior. > Especially if you imagine multiple users not even aware of each other. > Either the current "no records for mismatches" or the merged one make sense. Hence I had enlisted all the three available options.