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Thu, 6 Jun 2024 06:11:28 GMT Received: from [10.218.10.146] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 5 Jun 2024 23:11:22 -0700 Message-ID: <664cca91-8615-d3f6-7525-15b9b6725cce@quicinc.com> Date: Thu, 6 Jun 2024 11:41:19 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.11.2 Subject: Re: [PATCH V3 7/8] clk: qcom: Add GPUCC driver support for SM4450 To: Stephen Boyd , Dmitry Baryshkov CC: Michael Turquette , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Vladimir Zapolskiy , , , , , Taniya Das , Jagadeesh Kona , Imran Shaik , Satya Priya Kakitapalli References: <20240528114254.3147988-1-quic_ajipan@quicinc.com> <20240528114254.3147988-8-quic_ajipan@quicinc.com> <63d35ddacc113598f1822486b882552a.sboyd@kernel.org> Content-Language: en-US From: Ajit Pandey In-Reply-To: <63d35ddacc113598f1822486b882552a.sboyd@kernel.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: oz3MYEvDsO1nCe3XwPLEHzl9WDMbYrKr X-Proofpoint-GUID: oz3MYEvDsO1nCe3XwPLEHzl9WDMbYrKr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-06_01,2024-06-06_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 mlxscore=0 adultscore=0 bulkscore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 mlxlogscore=958 impostorscore=0 malwarescore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405170001 definitions=main-2406060044 On 5/30/2024 1:18 AM, Stephen Boyd wrote: > Quoting Dmitry Baryshkov (2024-05-28 06:23:27) >> On Tue, May 28, 2024 at 05:12:53PM +0530, Ajit Pandey wrote: >>> Add Graphics Clock Controller (GPUCC) support for SM4450 platform. >>> >>> Signed-off-by: Ajit Pandey >>> --- >>> drivers/clk/qcom/Kconfig | 9 + >>> drivers/clk/qcom/Makefile | 1 + >>> drivers/clk/qcom/gpucc-sm4450.c | 805 ++++++++++++++++++++++++++++++++ >>> 3 files changed, 815 insertions(+) >>> create mode 100644 drivers/clk/qcom/gpucc-sm4450.c >> >> [trimmed] >> >>> + >>> + /* Keep some clocks always enabled */ >>> + qcom_branch_set_clk_en(regmap, 0x93a4); /* GPU_CC_CB_CLK */ >>> + qcom_branch_set_clk_en(regmap, 0x9004); /* GPU_CC_CXO_AON_CLK */ >>> + qcom_branch_set_clk_en(regmap, 0x900c); /* GPU_CC_DEMET_CLK */ >> >> I pinged Stephen regarding these clocks. LGTM otherwise. >> > > Looks OK to me. I assume that these clks don't get turned off when the > GPU power domain is turned off. If that's the case then presumably we > would need to turn these on and off during power transitions. Yes, these clocks will not get turned off with GPU power domain transitions hence explicit on and off isn't required. -- Thanks, and Regards Ajit