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Message-ID: <17c9ef5c-068f-4ffa-a86f-1bacc75f2b78@linaro.org>
Date: Thu, 6 Jun 2024 09:29:27 +0200
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Subject: Re: [PATCH v3] usb: dwc3: enable CCI support for AMD-xilinx DWC3
 controller
To: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>,
 Thinh.Nguyen@synopsys.com, gregkh@linuxfoundation.org, michal.simek@amd.com,
 robh+dt@kernel.org
Cc: linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org,
 linux-arm-kernel@lists.infradead.org, git@amd.com
References: <1717657279-2631757-1-git-send-email-radhey.shyam.pandey@amd.com>
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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In-Reply-To: <1717657279-2631757-1-git-send-email-radhey.shyam.pandey@amd.com>
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On 06/06/2024 09:01, Radhey Shyam Pandey wrote:
> The GSBUSCFG0 register bits [31:16] are used to configure the cache type
> settings of the descriptor and data write/read transfers (Cacheable,
> Bufferable/Posted). When CCI is enabled in the design, DWC3 core GSBUSCFG0
> cache bits must be updated to support CCI enabled transfers in USB.
> 
> To program GSBUSCFG0 cache bits create a software node property
> in AMD-xilinx dwc3 glue driver and pass it to dwc3 core. The core
> then reads this property value and configures it in dwc3_core_init()
> sequence.
> 
> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
> ---
> Changes for v3:
> In v2 review as suggested by Thinh Nguyen, switch to swnode implementation
> for passing GSBUSCFG0 cache bits from AMD-xilinx dwc3 glue driver to
> core driver.
> 
> Changes for v2:
> Make GSBUSCFG0 configuration specific to AMD-xilinx platform.
> Taken reference from existing commit ec5eb43813a4 ("usb: dwc3: core:
> add support for realtek SoCs custom's global register start address")
> 
> v1 link:
> https://lore.kernel.org/all/20231013053448.11056-1-piyush.mehta@amd.com
> ---
>  drivers/usb/dwc3/core.c        | 24 ++++++++++++++++++++++++
>  drivers/usb/dwc3/core.h        |  8 ++++++++
>  drivers/usb/dwc3/dwc3-xilinx.c | 18 +++++++++++++++++-
>  3 files changed, 49 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index 7ee61a89520b..159d21b25629 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -23,6 +23,7 @@
>  #include <linux/delay.h>
>  #include <linux/dma-mapping.h>
>  #include <linux/of.h>
> +#include <linux/of_address.h>
>  #include <linux/of_graph.h>
>  #include <linux/acpi.h>
>  #include <linux/pinctrl/consumer.h>
> @@ -599,6 +600,19 @@ static void dwc3_cache_hwparams(struct dwc3 *dwc)
>  		parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9);
>  }
>  
> +static void dwc3_config_soc_bus(struct dwc3 *dwc)
> +{
> +	if (of_dma_is_coherent(dwc->dev->of_node)) {
> +		u32 reg;
> +
> +		reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
> +		reg &= ~DWC3_GSBUSCFG0_DAT_DES_RD_WR_REQINFO_MASK;
> +		reg |= (dwc->acache_data_rd_wr_info <<
> +			DWC3_GSBUSCFG0_DAT_DES_RD_WR_REQINFO_SHIFT);
> +		dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg);
> +	}
> +}
> +
>  static int dwc3_core_ulpi_init(struct dwc3 *dwc)
>  {
>  	int intf;
> @@ -1320,6 +1334,8 @@ static int dwc3_core_init(struct dwc3 *dwc)
>  
>  	dwc3_set_incr_burst_type(dwc);
>  
> +	dwc3_config_soc_bus(dwc);
> +
>  	ret = dwc3_phy_power_on(dwc);
>  	if (ret)
>  		goto err_exit_phy;
> @@ -1574,6 +1590,7 @@ static void dwc3_get_properties(struct dwc3 *dwc)
>  	u8			tx_max_burst_prd = 0;
>  	u8			tx_fifo_resize_max_num;
>  	const char		*usb_psy_name;
> +	struct device		*tmpdev;
>  	int			ret;
>  
>  	/* default to highest possible threshold */
> @@ -1716,6 +1733,13 @@ static void dwc3_get_properties(struct dwc3 *dwc)
>  	dwc->dis_split_quirk = device_property_read_bool(dev,
>  				"snps,dis-split-quirk");
>  
> +	/* Iterate over all parent nodes for finding swnode properties */

And:
/* non-DT (non-ABI) properties */

so someone will not try to make it ABI post-factum.


Best regards,
Krzysztof