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From: Biju Das <biju.das.jz@bp.renesas.com>
To: Prabhakar <prabhakar.csengg@gmail.com>, Geert Uytterhoeven
	<geert+renesas@glider.be>, Ulf Hansson <ulf.hansson@linaro.org>, Rob Herring
	<robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley
	<conor+dt@kernel.org>, Wolfram Sang <wsa+renesas@sang-engineering.com>, Liam
 Girdwood <lgirdwood@gmail.com>, Mark Brown <broonie@kernel.org>, Magnus Damm
	<magnus.damm@gmail.com>
CC: "linux-mmc@vger.kernel.org" <linux-mmc@vger.kernel.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-renesas-soc@vger.kernel.org" <linux-renesas-soc@vger.kernel.org>,
	Fabrizio Castro <fabrizio.castro.jz@renesas.com>, Prabhakar Mahadev Lad
	<prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: RE: [RFC PATCH 4/4] mmc: renesas_sdhi: Add support for RZ/V2H(P) SoC
Thread-Topic: [RFC PATCH 4/4] mmc: renesas_sdhi: Add support for RZ/V2H(P) SoC
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Date: Thu, 6 Jun 2024 09:32:12 +0000
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Hi Prabhakar,

Thanks for the feedback.

> -----Original Message-----
> From: Prabhakar <prabhakar.csengg@gmail.com>
> Sent: Wednesday, June 5, 2024 8:50 AM
> Subject: [RFC PATCH 4/4] mmc: renesas_sdhi: Add support for RZ/V2H(P) SoC
>=20
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>=20
> The SDHI/eMMC IPs found in the RZ/V2H(P) (a.k.a. r9a09g057) are very simi=
lar to those found in R-
> Car Gen3. However, they are not identical, necessitating an SoC-specific =
compatible string for
> fine-tuning driver support.
>=20
> Key features of the RZ/V2H(P) SDHI/eMMC IPs include:
> - Voltage level control via the IOVS bit.
> - PWEN pin support via SD_STATUS register.
> - Lack of HS400 support.
> - Fixed address mode operation.
>=20
> sd_iovs and sd_pwen quirks are introduced for SoCs supporting this bit to=
 handle voltage level
> control and power enable via SD_STATUS register.
>=20
> regulator support is added to control the volatage levels of SD pins via =
sd_iovs bit in SD_STATUS
> register.
>=20
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
>  drivers/mmc/host/renesas_sdhi.h               |  7 ++
>  drivers/mmc/host/renesas_sdhi_core.c          | 67 +++++++++++++++++--
>  drivers/mmc/host/renesas_sdhi_internal_dmac.c | 45 +++++++++++++
>  drivers/mmc/host/tmio_mmc.h                   |  4 ++
>  4 files changed, 118 insertions(+), 5 deletions(-)
>=20
> diff --git a/drivers/mmc/host/renesas_sdhi.h b/drivers/mmc/host/renesas_s=
dhi.h index
> 586f94d4dbfd..9ef4fdf44280 100644
> --- a/drivers/mmc/host/renesas_sdhi.h
> +++ b/drivers/mmc/host/renesas_sdhi.h
> @@ -11,6 +11,8 @@
>=20
>  #include <linux/dmaengine.h>
>  #include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/regulator/driver.h>
>  #include "tmio_mmc.h"
>=20
>  struct renesas_sdhi_scc {
> @@ -49,6 +51,11 @@ struct renesas_sdhi_quirks {
>  	bool manual_tap_correction;
>  	bool old_info1_layout;
>  	u32 hs400_bad_taps;
> +	bool sd_iovs;
> +	bool sd_pwen;
> +	struct regulator_desc *rdesc;
> +	const struct regmap_config *rdesc_regmap_config;
> +	unsigned int rdesc_offset;
>  	const u8 (*hs400_calib_table)[SDHI_CALIB_TABLE_MAX];
>  };
>=20
> diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/rene=
sas_sdhi_core.c
> index 12f4faaaf4ee..2eeea9513a23 100644
> --- a/drivers/mmc/host/renesas_sdhi_core.c
> +++ b/drivers/mmc/host/renesas_sdhi_core.c
> @@ -248,6 +248,19 @@ static int renesas_sdhi_card_busy(struct mmc_host *m=
mc)
>  		 TMIO_STAT_DAT0);
>  }
>=20
> +static void renesas_sdhi_sd_status_pwen(struct tmio_mmc_host *host,
> +bool on) {
> +	u32 sd_status;
> +
> +	sd_ctrl_read32_rep(host, CTL_SD_STATUS, &sd_status, 1);
> +	if (on)
> +		sd_status |=3D  SD_STATUS_PWEN;
> +	else
> +		sd_status &=3D  ~SD_STATUS_PWEN;
> +
> +	sd_ctrl_write32(host, CTL_SD_STATUS, sd_status); }
> +

May be use regulator_set_voltage() to set this??

>  static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc=
,
>  						    struct mmc_ios *ios)
>  {
> @@ -587,6 +600,9 @@ static void renesas_sdhi_reset(struct tmio_mmc_host *=
host, bool preserve)
>  					  false, priv->rstc);
>  			/* At least SDHI_VER_GEN2_SDR50 needs manual release of reset */
>  			sd_ctrl_write16(host, CTL_RESET_SD, 0x0001);
> +			if (sdhi_has_quirk(priv, sd_pwen))
> +				renesas_sdhi_sd_status_pwen(host, true);
> +
>  			priv->needs_adjust_hs400 =3D false;
>  			renesas_sdhi_set_clock(host, host->clk_cache);
>=20
> @@ -904,6 +920,34 @@ static void renesas_sdhi_enable_dma(struct tmio_mmc_=
host *host, bool enable)
>  	renesas_sdhi_sdbuf_width(host, enable ? width : 16);  }
>=20
> +static int renesas_sdhi_internal_dmac_register_regulator(struct platform=
_device *pdev,
> +							 const struct renesas_sdhi_quirks *quirks) {
> +	struct tmio_mmc_host *host =3D platform_get_drvdata(pdev);
> +	struct renesas_sdhi *priv =3D host_to_priv(host);
> +	struct regulator_config rcfg =3D {
> +		.dev =3D &pdev->dev,
> +		.driver_data =3D priv,
> +	};
> +	struct regulator_dev *rdev;
> +	const char *devname;
> +
> +	devname =3D devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s-vqmmc-regulator"=
,
> +				 dev_name(&pdev->dev));
> +	if (!devname)
> +		return -ENOMEM;
> +
> +	quirks->rdesc->name =3D devname;
> +	rcfg.regmap =3D devm_regmap_init_mmio(&pdev->dev, host->ctl + quirks->r=
desc_offset,

This is (CTL_SD_STATUS << 2) , so the variable can be dropped from quirks.

Cheers,
Biju

> +					    quirks->rdesc_regmap_config);
> +	if (IS_ERR(rcfg.regmap))
> +		return PTR_ERR(rcfg.regmap);
> +
> +	rdev =3D devm_regulator_register(&pdev->dev, quirks->rdesc, &rcfg);
> +
> +	return PTR_ERR_OR_ZERO(rdev);
> +}
> +
>  int renesas_sdhi_probe(struct platform_device *pdev,
>  		       const struct tmio_mmc_dma_ops *dma_ops,
>  		       const struct renesas_sdhi_of_data *of_data, @@ -1051,6 +1095,15=
 @@ int
> renesas_sdhi_probe(struct platform_device *pdev,
>  	if (ret)
>  		goto efree;
>=20
> +	if (sdhi_has_quirk(priv, sd_iovs)) {
> +		ret =3D renesas_sdhi_internal_dmac_register_regulator(pdev, quirks);
> +		if (ret)
> +			goto efree;
> +	}
> +
> +	if (sdhi_has_quirk(priv, sd_pwen))
> +		renesas_sdhi_sd_status_pwen(host, true);
> +
>  	ver =3D sd_ctrl_read16(host, CTL_VERSION);
>  	/* GEN2_SDR104 is first known SDHI to use 32bit block count */
>  	if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX) @@=
 -1110,26 +1163,26 @@
> int renesas_sdhi_probe(struct platform_device *pdev,
>  	num_irqs =3D platform_irq_count(pdev);
>  	if (num_irqs < 0) {
>  		ret =3D num_irqs;
> -		goto eirq;
> +		goto epwen;
>  	}
>=20
>  	/* There must be at least one IRQ source */
>  	if (!num_irqs) {
>  		ret =3D -ENXIO;
> -		goto eirq;
> +		goto epwen;
>  	}
>=20
>  	for (i =3D 0; i < num_irqs; i++) {
>  		irq =3D platform_get_irq(pdev, i);
>  		if (irq < 0) {
>  			ret =3D irq;
> -			goto eirq;
> +			goto epwen;
>  		}
>=20
>  		ret =3D devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0,
>  				       dev_name(&pdev->dev), host);
>  		if (ret)
> -			goto eirq;
> +			goto epwen;
>  	}
>=20
>  	ret =3D tmio_mmc_host_probe(host);
> @@ -1141,7 +1194,9 @@ int renesas_sdhi_probe(struct platform_device *pdev=
,
>=20
>  	return ret;
>=20
> -eirq:
> +epwen:
> +	if (sdhi_has_quirk(priv, sd_pwen))
> +		renesas_sdhi_sd_status_pwen(host, false);
>  	tmio_mmc_host_remove(host);
>  edisclk:
>  	renesas_sdhi_clk_disable(host);
> @@ -1157,6 +1212,8 @@ void renesas_sdhi_remove(struct platform_device *pd=
ev)
>  	struct tmio_mmc_host *host =3D platform_get_drvdata(pdev);
>=20
>  	tmio_mmc_host_remove(host);
> +	if (sdhi_has_quirk(host_to_priv(host), sd_pwen))
> +		renesas_sdhi_sd_status_pwen(host, false);
>  	renesas_sdhi_clk_disable(host);
>  	tmio_mmc_host_free(host);
>  }
> diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
> b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
> index 422fa63a2e99..f824d167bb09 100644
> --- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
> +++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
> @@ -215,6 +215,45 @@ static const struct renesas_sdhi_quirks sdhi_quirks_=
rzg2l =3D {
>  	.hs400_disabled =3D true,
>  };
>=20
> +static const unsigned int r9a09g057_vqmmc_voltages[] =3D {
> +	3300000, 1800000,
> +};
> +
> +static const struct regulator_ops r9a09g057_regulator_voltage_ops =3D {
> +	.list_voltage =3D regulator_list_voltage_table,
> +	.map_voltage =3D regulator_map_voltage_descend,
> +	.get_voltage_sel =3D regulator_get_voltage_sel_regmap,
> +	.set_voltage_sel =3D regulator_set_voltage_sel_regmap, };
> +
> +static struct regulator_desc r9a09g057_vqmmc_regulator =3D {
> +	.of_match	=3D of_match_ptr("vqmmc-r9a09g057-regulator"),
> +	.owner		=3D THIS_MODULE,
> +	.type		=3D REGULATOR_VOLTAGE,
> +	.ops		=3D &r9a09g057_regulator_voltage_ops,
> +	.volt_table	=3D r9a09g057_vqmmc_voltages,
> +	.n_voltages	=3D ARRAY_SIZE(r9a09g057_vqmmc_voltages),
> +	.vsel_mask	=3D 0x10000,
> +	.vsel_reg	=3D 0,
> +};
> +
> +static const struct regmap_config r9a09g057_vqmmc_regmap_config =3D {
> +	.reg_bits	=3D 32,
> +	.val_bits	=3D 32,
> +	.reg_stride	=3D 4,
> +	.max_register	=3D 1,
> +};
> +
> +static const struct renesas_sdhi_quirks sdhi_quirks_r9a09g057 =3D {
> +	.fixed_addr_mode =3D true,
> +	.hs400_disabled =3D true,
> +	.sd_iovs =3D true,
> +	.sd_pwen =3D true,
> +	.rdesc =3D &r9a09g057_vqmmc_regulator,
> +	.rdesc_regmap_config =3D &r9a09g057_vqmmc_regmap_config,
> +	.rdesc_offset =3D 0x3C8,
> +};
> +
>  /*
>   * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of=
 now.
>   * So, we want to treat them equally and only have a match for ES1.2 to =
enforce @@ -260,6 +299,11
> @@ static const struct renesas_sdhi_of_data_with_quirks of_rzg2l_compatib=
le =3D {
>  	.quirks =3D &sdhi_quirks_rzg2l,
>  };
>=20
> +static const struct renesas_sdhi_of_data_with_quirks of_r9a09g057_compat=
ible =3D {
> +	.of_data =3D &of_data_rcar_gen3,
> +	.quirks =3D &sdhi_quirks_r9a09g057,
> +};
> +
>  static const struct renesas_sdhi_of_data_with_quirks of_rcar_gen3_compat=
ible =3D {
>  	.of_data =3D &of_data_rcar_gen3,
>  };
> @@ -284,6 +328,7 @@ static const struct of_device_id renesas_sdhi_interna=
l_dmac_of_match[] =3D {
>  	{ .compatible =3D "renesas,sdhi-r8a77990", .data =3D &of_r8a77990_compa=
tible, },
>  	{ .compatible =3D "renesas,sdhi-r8a77995", .data =3D &of_rcar_gen3_nohs=
400_compatible, },
>  	{ .compatible =3D "renesas,sdhi-r9a09g011", .data =3D &of_rzg2l_compati=
ble, },
> +	{ .compatible =3D "renesas,sdhi-r9a09g057", .data =3D
> +&of_r9a09g057_compatible, },
>  	{ .compatible =3D "renesas,rzg2l-sdhi", .data =3D &of_rzg2l_compatible,=
 },
>  	{ .compatible =3D "renesas,rcar-gen3-sdhi", .data =3D &of_rcar_gen3_com=
patible, },
>  	{ .compatible =3D "renesas,rcar-gen4-sdhi", .data =3D &of_rcar_gen3_com=
patible, }, diff --git
> a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h index de56e65=
34aea..d03aedf61aa3 100644
> --- a/drivers/mmc/host/tmio_mmc.h
> +++ b/drivers/mmc/host/tmio_mmc.h
> @@ -43,6 +43,7 @@
>  #define CTL_RESET_SD 0xe0
>  #define CTL_VERSION 0xe2
>  #define CTL_SDIF_MODE 0xe6 /* only known on R-Car 2+ */
> +#define CTL_SD_STATUS 0xf2 /* only known on RZ/G2L and RZ/V2H(P) */
>=20
>  /* Definitions for values the CTL_STOP_INTERNAL_ACTION register can take=
 */
>  #define TMIO_STOP_STP		BIT(0)
> @@ -102,6 +103,9 @@
>  /* Definitions for values the CTL_SDIF_MODE register can take */
>  #define SDIF_MODE_HS400		BIT(0) /* only known on R-Car 2+ */
>=20
> +/* Definitions for values the CTL_SD_STATUS register can take */
> +#define SD_STATUS_PWEN		BIT(0) /* only known on RZ/V2H(P) */
> +
>  /* Define some IRQ masks */
>  /* This is the mask used at reset by the chip */
>  #define TMIO_MASK_ALL           0x837f031d
> --
> 2.34.1