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From: Heiko =?ISO-8859-1?Q?St=FCbner?= <heiko@sntech.de>
To: Linus Walleij <linus.walleij@linaro.org>, Huang-Huang Bao <i@eh5.me>
Cc: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
 linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
 Huang-Huang Bao <i@eh5.me>
Subject: Re: [PATCH 1/3] pinctrl: rockchip: fix RK3328 pinmux bits
Date: Thu, 06 Jun 2024 12:08:34 +0200
Message-ID: <3862456.FjKLVJYuhi@diego>
In-Reply-To: <20240606060435.765716-2-i@mail.eh5.me>
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 <20240606060435.765716-1-i@eh5.me> <20240606060435.765716-2-i@mail.eh5.me>
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Hi,

Am Donnerstag, 6. Juni 2024, 08:04:33 CEST schrieb Huang-Huang Bao:
> The pinmux bits for GPIO2-B0 to GPIO2-B6 actually have 2 bits width,
> correct the bank flag for GPIO2-B. The pinmux bits for GPIO2-B7 is
> recalculated so it remain unchanged.

I've verified the gpio2-related pin settings via the TRM, so this part
looks good :-)


> The pinmux bits for GPIO3-B1 to GPIO3-B6 have different register offset
> than common rockhip pinmux, set the correct value for those pins in
> rk3328_mux_recalced_data.
> 
> The pinmux bits for those pins are not explicitly specified in RK3328
> TRM, however we can get hint from pad name and its correspinding IOMUX
> setting for pins in interface descriptions, e.g.
> IO_SPIclkm0_GPIO2B0vccio5 with GRF_GPIO2B_IOMUX[1:0]=2'b01 setting.
> 
> This fix has been tested on NanoPi R2S for fixing confliting pinmux bits
> between GPIO2-15 with GPIO2-13.

As you said, the gpio3-based pins are not documented in the TRM,
but in your description above you're talking about pins in the gpio2-
group?

So where did the gpio3-related pin information come from?

Also, could you please split this patch in two pieces, one fixing the
gpio2-area and one for the new gpio3 pins please?


Thanks
Heiko

> Signed-off-by: Huang-Huang Bao <i@eh5.me>
> ---
>  drivers/pinctrl/pinctrl-rockchip.c | 59 ++++++++++++++++++++++++++----
>  1 file changed, 52 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
> index 3bedf36a0019..23531ea0d088 100644
> --- a/drivers/pinctrl/pinctrl-rockchip.c
> +++ b/drivers/pinctrl/pinctrl-rockchip.c
> @@ -634,23 +634,68 @@ static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
>  
>  static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
>  	{
> -		.num = 2,
> -		.pin = 12,
> -		.reg = 0x24,
> -		.bit = 8,
> -		.mask = 0x3
> -	}, {
> +		/* gpio2_b7_sel */
>  		.num = 2,
>  		.pin = 15,
>  		.reg = 0x28,
>  		.bit = 0,
>  		.mask = 0x7
>  	}, {
> +		/* gpio2_c7_sel */
>  		.num = 2,
>  		.pin = 23,
>  		.reg = 0x30,
>  		.bit = 14,
>  		.mask = 0x3
> +	}, {
> +		/* gpio3_b1_sel */
> +		.num = 3,
> +		.pin = 9,
> +		.reg = 0x44,
> +		.bit = 2,
> +		.mask = 0x3
> +	}, {
> +		/* gpio3_b2_sel */
> +		.num = 3,
> +		.pin = 10,
> +		.reg = 0x44,
> +		.bit = 4,
> +		.mask = 0x3
> +	}, {
> +		/* gpio3_b3_sel */
> +		.num = 3,
> +		.pin = 11,
> +		.reg = 0x44,
> +		.bit = 6,
> +		.mask = 0x3
> +	}, {
> +		/* gpio3_b4_sel */
> +		.num = 3,
> +		.pin = 12,
> +		.reg = 0x44,
> +		.bit = 8,
> +		.mask = 0x3
> +	}, {
> +		/* gpio3_b5_sel */
> +		.num = 3,
> +		.pin = 13,
> +		.reg = 0x44,
> +		.bit = 10,
> +		.mask = 0x3
> +	}, {
> +		/* gpio3_b6_sel */
> +		.num = 3,
> +		.pin = 14,
> +		.reg = 0x44,
> +		.bit = 12,
> +		.mask = 0x3
> +	}, {
> +		/* gpio3_b7_sel */
> +		.num = 3,
> +		.pin = 15,
> +		.reg = 0x44,
> +		.bit = 14,
> +		.mask = 0x3
>  	},
>  };
>  
> @@ -3763,7 +3808,7 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = {
>  	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
>  	PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
>  	PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
> -			     IOMUX_WIDTH_3BIT,
> +			     0,
>  			     IOMUX_WIDTH_3BIT,
>  			     0),
>  	PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
>