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From: "Swathi K S" <swathi.ks@samsung.com>
To: "'Krzysztof Kozlowski'" <krzysztof.kozlowski@linaro.org>,
	<davem@davemloft.net>, <edumazet@google.com>, <kuba@kernel.org>,
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	<krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>,
	<richardcochran@gmail.com>, <alexandre.torgue@foss.st.com>,
	<joabreu@synopsys.com>, <mcoquelin.stm32@gmail.com>,
	<alim.akhtar@samsung.com>, <linux-fsd@tesla.com>,
	<pankaj.dubey@samsung.com>, <ravi.patel@samsung.com>
Cc: <netdev@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <linux-samsung-soc@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>, "'Chandrasekar R'"
	<rcsekar@samsung.com>, "'Suresh Siddha'" <ssiddha@tesla.com>
In-Reply-To: <baa64cff-885a-2ecb-8a0f-3b820e55e1b8@linaro.org>
Subject: RE: [PATCH v3 2/4] net: stmmac: dwc-qos: Add FSD EQoS support
Date: Thu, 6 Jun 2024 14:44:40 +0530
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> -----Original Message-----
> From: Krzysztof Kozlowski =5Bmailto:krzysztof.kozlowski=40linaro.org=5D
> Sent: 18 August 2023 14:57
> To: Sriranjani P <sriranjani.p=40samsung.com>; davem=40davemloft.net;
> edumazet=40google.com; kuba=40kernel.org; pabeni=40redhat.com;
> robh+dt=40kernel.org; krzysztof.kozlowski+dt=40linaro.org;
> conor+dt=40kernel.org; richardcochran=40gmail.com;
> alexandre.torgue=40foss.st.com; joabreu=40synopsys.com;
> mcoquelin.stm32=40gmail.com; alim.akhtar=40samsung.com; linux-
> fsd=40tesla.com; pankaj.dubey=40samsung.com; swathi.ks=40samsung.com;
> ravi.patel=40samsung.com
> Cc: netdev=40vger.kernel.org; devicetree=40vger.kernel.org; linux-
> kernel=40vger.kernel.org; linux-samsung-soc=40vger.kernel.org; linux-arm-
> kernel=40lists.infradead.org; 'Chandrasekar R' <rcsekar=40samsung.com>;
> 'Suresh Siddha' <ssiddha=40tesla.com>
> Subject: Re: =5BPATCH v3 2/4=5D net: stmmac: dwc-qos: Add FSD EQoS suppor=
t
>=20
> On 16/08/2023 08:38, Sriranjani P wrote:
> >
> >
> >> -----Original Message-----
> >> From: Krzysztof Kozlowski =5Bmailto:krzysztof.kozlowski=40linaro.org=
=5D
> >> Sent: 15 August 2023 01:21
> >> To: Sriranjani P <sriranjani.p=40samsung.com>; davem=40davemloft.net;
> >> edumazet=40google.com; kuba=40kernel.org; pabeni=40redhat.com;
> >> robh+dt=40kernel.org; krzysztof.kozlowski+dt=40linaro.org;
> >> conor+dt=40kernel.org; richardcochran=40gmail.com;
> >> alexandre.torgue=40foss.st.com; joabreu=40synopsys.com;
> >> mcoquelin.stm32=40gmail.com; alim.akhtar=40samsung.com; linux-
> >> fsd=40tesla.com; pankaj.dubey=40samsung.com; swathi.ks=40samsung.com;
> >> ravi.patel=40samsung.com
> >> Cc: netdev=40vger.kernel.org; devicetree=40vger.kernel.org; linux-
> >> kernel=40vger.kernel.org; linux-samsung-soc=40vger.kernel.org; linux-a=
rm-
> >> kernel=40lists.infradead.org; Chandrasekar R <rcsekar=40samsung.com>;
> >> Suresh Siddha <ssiddha=40tesla.com>
> >> Subject: Re: =5BPATCH v3 2/4=5D net: stmmac: dwc-qos: Add FSD EQoS
> >> support
> >>
> >> On 14/08/2023 13:25, Sriranjani P wrote:
> >>> The FSD SoC contains two instance of the Synopsys DWC ethernet QOS
> >>> IP
> >> core.
> >>> The binding that it uses is slightly different from existing ones
> >>> because of the integration (clocks, resets).
> >>>
> >>> For FSD SoC, a mux switch is needed between internal and external
> clocks.
> >>> By default after reset internal clock is used but for receiving
> >>> packets properly, external clock is needed. Mux switch to external
> >>> clock happens only when the external clock is present.
> >>>
> >>> Signed-off-by: Chandrasekar R <rcsekar=40samsung.com>
> >>> Signed-off-by: Suresh Siddha <ssiddha=40tesla.com>
> >>> Signed-off-by: Swathi K S <swathi.ks=40samsung.com>
> >>> Signed-off-by: Sriranjani P <sriranjani.p=40samsung.com>
> >>> ---
> >>
> >>
> >>> +static int dwc_eqos_setup_rxclock(struct platform_device *pdev, int
> >>> +ins_num) =7B
> >>> +	struct device_node *np =3D pdev->dev.of_node;
> >>> +	struct regmap *syscon;
> >>> +	unsigned int reg;
> >>> +
> >>> +	if (np && of_property_read_bool(np, =22fsd-rx-clock-skew=22)) =7B
> >>> +		syscon =3D syscon_regmap_lookup_by_phandle_args(np,
> >>> +							      =22fsd-rx-clock-
> >> skew=22,
> >>> +							      1, &reg);
> >>> +		if (IS_ERR(syscon)) =7B
> >>> +			dev_err(&pdev->dev,
> >>> +				=22couldn't get the rx-clock-skew syscon=21=5Cn=22);
> >>> +			return PTR_ERR(syscon);
> >>> +		=7D
> >>> +
> >>> +		regmap_write(syscon, reg, rx_clock_skew_val=5Bins_num=5D);
> >>> +	=7D
> >>> +
> >>> +	return 0;
> >>> +=7D
> >>> +
> >>> +static int fsd_eqos_clk_init(struct fsd_eqos_plat_data *plat,
> >>> +			     struct plat_stmmacenet_data *data) =7B
> >>> +	int ret =3D 0, i;
> >>> +
> >>> +	const struct fsd_eqos_variant *fsd_eqos_v_data =3D
> >>> +						plat->fsd_eqos_inst_var;
> >>> +
> >>> +	plat->clks =3D devm_kcalloc(plat->dev, fsd_eqos_v_data->num_clks,
> >>> +				  sizeof(*plat->clks), GFP_KERNEL);
> >>> +	if (=21plat->clks)
> >>> +		return -ENOMEM;
> >>> +
> >>> +	for (i =3D 0; i < fsd_eqos_v_data->num_clks; i++)
> >>> +		plat->clks=5Bi=5D.id =3D fsd_eqos_v_data->clk_list=5Bi=5D;
> >>> +
> >>> +	ret =3D devm_clk_bulk_get(plat->dev, fsd_eqos_v_data->num_clks,
> >>> +				plat->clks);
> >>
> >> Instead of duplicating entire clock management with existing code,
> >> you should extend/rework existing one.
> >>
> >> This code is unfortunately great example how not to stuff vendor code
> >> into upstream project. :(
> >
> > I will check again if I can extend existing one to support FSD platform
> specific requirement.
> >
> >>
> >>> +
> >>> +	return ret;
> >>> +=7D
> >>> +
> >>> +static int fsd_clks_endisable(void *priv, bool enabled) =7B
> >>> +	int ret, num_clks;
> >>> +	struct fsd_eqos_plat_data *plat =3D priv;
> >>> +
> >>> +	num_clks =3D plat->fsd_eqos_inst_var->num_clks;
> >>> +
> >>> +	if (enabled) =7B
> >>> +		ret =3D clk_bulk_prepare_enable(num_clks, plat->clks);
> >>> +		if (ret) =7B
> >>> +			dev_err(plat->dev, =22Clock enable failed, err =3D %d=5Cn=22,
> >> ret);
> >>> +			return ret;
> >>> +		=7D
> >>> +	=7D else =7B
> >>> +		clk_bulk_disable_unprepare(num_clks, plat->clks);
> >>> +	=7D
> >>> +
> >>> +	return 0;
> >>> +=7D
> >>> +
> >>> +static int fsd_eqos_probe(struct platform_device *pdev,
> >>> +			  struct plat_stmmacenet_data *data,
> >>> +			  struct stmmac_resources *res)
> >>> +=7B
> >>> +	struct fsd_eqos_plat_data *priv_plat;
> >>> +	struct device_node *np =3D pdev->dev.of_node;
> >>> +	int ret =3D 0;
> >>> +
> >>> +	priv_plat =3D devm_kzalloc(&pdev->dev, sizeof(*priv_plat),
> >> GFP_KERNEL);
> >>> +	if (=21priv_plat) =7B
> >>> +		ret =3D -ENOMEM;
> >>
> >> return -ENOMEM
> >
> > Will fix this in v4.
> >
> >>
> >>> +		goto error;
> >>> +	=7D
> >>> +
> >>> +	priv_plat->dev =3D &pdev->dev;
> >>> +	data->bus_id =3D of_alias_get_id(np, =22eth=22);
> >>
> >> No, you cannot do like this. Aliases are board specific and are based
> >> on labeling on the board.
> >
> > So if I understood this correctly, I need to move alias in the board
> > specific DTS file
>=20
> This part: yes
>=20
> > and I can use this, because we have to handle rx-clock-skew differently=
 for
> the two instances in the FSD platform.
>=20
> Not really. Do you expect it to work correctly if given EQoS instance rec=
eives
> different alias, e.g. 5?
>=20
> > Another approach we took in v1, by specifying the value to be programme=
d
> in rx-clock-skew property itself, but it seems it is not a preferred appr=
oach.
> > I can see that in drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
> +436 common code is already using this API and getting alias id, so I can
> probably use the same rather getting same again here, but I have to speci=
fy
> alias in DTS file.
>=20
> Getting alias ID is okay in general. It is used to provide user-visible I=
D of the
> devices (see mmc). Using such alias to configure hardware is abuse of the
> alias, because of the reasons I said - how is it supposed to work if alia=
s is 5
> (this is perfectly valid alias)?
>=20
> I suspect that all this is to substitute missing abstractions, like clock=
s, phys or
> resets...

Will avoid using the API to get alias id to configure the HW. Will share th=
e new implementation in v4.

>=20
> Best regards,
> Krzysztof


Regards,
Swathi