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Message-ID: <202852cb-d49e-4380-8073-8bb679fcf53e@linaro.org>
Date: Thu, 6 Jun 2024 13:27:34 +0200
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Subject: Re: [PATCH v3 2/5] clk: qcom: clk-alpha-pll: Add HUAYRA_2290 support
To: Stephen Boyd <sboyd@kernel.org>, Bjorn Andersson <andersson@kernel.org>,
 Conor Dooley <conor+dt@kernel.org>,
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
 Michael Turquette <mturquette@baylibre.com>, Rob Herring <robh@kernel.org>
Cc: Marijn Suijten <marijn.suijten@somainline.org>,
 Konrad Dybcio <konradybcio@kernel.org>, linux-arm-msm@vger.kernel.org,
 linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
 linux-kernel@vger.kernel.org, Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
References: <20240219-topic-rb1_gpu-v3-0-86f67786539a@linaro.org>
 <20240219-topic-rb1_gpu-v3-2-86f67786539a@linaro.org>
 <b39e9d5ecfddef7b0564c2224685d9d0.sboyd@kernel.org>
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From: Konrad Dybcio <konrad.dybcio@linaro.org>
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In-Reply-To: <b39e9d5ecfddef7b0564c2224685d9d0.sboyd@kernel.org>
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On 5.04.2024 11:37 PM, Stephen Boyd wrote:
> Quoting Konrad Dybcio (2024-03-26 14:08:24)
>> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
>> index 8a412ef47e16..27ba8aa3e577 100644
>> --- a/drivers/clk/qcom/clk-alpha-pll.c
>> +++ b/drivers/clk/qcom/clk-alpha-pll.c
>> @@ -779,6 +792,40 @@ static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate,
>>         return clamp(rate, min_freq, max_freq);
>>  }
>>  
>> +void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
>> +                                  const struct alpha_pll_config *config)
>> +{
>> +       u32 val;
>> +
>> +       clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
>> +       clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
>> +       clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
>> +       clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
>> +       clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
>> +       clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
>> +       clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
>> +       clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
>> +       clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
>> +
>> +       /* Set PLL_BYPASSNL */
>> +       regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL);
>> +       regmap_read(regmap, PLL_MODE(pll), &val);
>> +
>> +       /* Wait 5 us between setting BYPASS and deasserting reset */
>> +       udelay(5);
>> +
>> +       /* Take PLL out from reset state */
>> +       regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
>> +       regmap_read(regmap, PLL_MODE(pll), &val);
>> +
>> +       /* Wait 50us for PLL_LOCK_DET bit to go high */
> 
> Is the bit not reliable or something? I'd expect to see a polling loop
> here but it's a sleep.

Unfortunately, it seems so.

Konrad