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[209.85.219.179]) by smtp.gmail.com with ESMTPSA id 00721157ae682-62ccacadca4sm2206077b3.18.2024.06.06.04.57.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 06 Jun 2024 04:57:51 -0700 (PDT) Received: by mail-yb1-f179.google.com with SMTP id 3f1490d57ef6-dfa682a4025so980579276.2; Thu, 06 Jun 2024 04:57:51 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCVQ+Ev+Dh+oGOrZAosHwR+5gDEIXkzerjoINl5nb/M6B+bkkTKBII7AlCcF/h/PkyAp06mxs2E6QBPhovLD9O6BUVix8sBmoQQHv9IJLojhgS3/LTFnCqz0hBD9mOVBQ7riTj/yy4WDRNgyPTRys58+44oGQBwJsPIZfes+qIj+RgRqpmvvUYVjtIMaMMG0jp3URVtJqcdGMOh/qFlJYc8g1DNRoCmiQQ== X-Received: by 2002:a5b:64b:0:b0:dfa:7bcd:efc0 with SMTP id 3f1490d57ef6-dfacacec42bmr5433758276.43.1717675071297; Thu, 06 Jun 2024 04:57:51 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240606085133.632307-1-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20240606085133.632307-1-prabhakar.mahadev-lad.rj@bp.renesas.com> From: Geert Uytterhoeven Date: Thu, 6 Jun 2024 13:57:39 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4] dt-bindings: pinctrl: renesas: Document RZ/V2H(P) SoC To: Prabhakar Cc: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fabrizio Castro , Lad Prabhakar Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, Jun 6, 2024 at 10:51=E2=80=AFAM Prabhakar wrote: > From: Lad Prabhakar > > Add documentation for the pin controller found on the Renesas RZ/V2H(P) > (R9A09G057) SoC. The RZ/V2H PFC varies slightly compared to the RZ/G2L > family: > - Additional bits need to be set during pinmuxing. > - The GPIO pin count is different. > > Hence, a SoC-specific compatible string, 'renesas,r9a09g057-pinctrl', is > added for the RZ/V2H(P) SoC. > > Also, add the 'renesas,output-impedance' property. The drive strength > setting on RZ/V2H(P) depends on the different power rails coming out from > the PMIC (connected via I2C). These power rails (required for drive > strength) can be 1.2V, 1.8V, or 3.3V. > > Pins are grouped into 4 groups: > > Group 1: Impedance > - 150/75/38/25 ohms (at 3.3V) > - 130/65/33/22 ohms (at 1.8V) > > Group 2: Impedance > - 50/40/33/25 ohms (at 1.8V) > > Group 3: Impedance > - 150/75/37.5/25 ohms (at 3.3V) > - 130/65/33/22 ohms (at 1.8V) > > Group 4: Impedance > - 110/55/30/20 ohms (at 1.8V) > - 150/75/38/25 ohms (at 1.2V) > > The 'renesas,output-impedance' property, as documented, can be > [0, 1, 2, 3], these correspond to register bit values that can > be set in the PFC_IOLH_mn register, which adjusts the drive > strength value and is pin-dependent. > > As power rail information may not be available very early in the boot > process, the 'renesas,output-impedance' property is added instead of > reusing the 'output-impedance-ohms' property. > > Also, allow bias-disable, bias-pull-down and bias-pull-up properties > as these can be used to configure the pins. > > Signed-off-by: Lad Prabhakar > --- > Sending just the binding patch of series [0] as reset of the patches have > been Reviewed. > > [0] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20240530= 173857.164073-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ > > v3->v4 > - Added a conditional schema for ensuring the reset length > is 2 for RZ/V2H and 3 otherwise > - Updated description for renesas,output-impedance property > - Dropped '|' Reviewed-by: Geert Uytterhoeven i.e. will queue in renesas-pinctrl for v6.11. Gr{oetje,eeting}s, Geert --=20 Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k= .org In personal conversations with technical people, I call myself a hacker. Bu= t when I'm talking to journalists I just say "programmer" or something like t= hat. -- Linus Torvalds