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AJvYcCX3KcaqVM79QSeggliMrEGDMjMWN0olQBdLL4YAlCrlk+DQ/c0fgtzowyS9HIYfu2FyEVFCZjqhBi2eDwpnMlDRIxWDGgfD1Oc7htty5MCNU53aZiSuBuI8Uq+KHD0LyqYRQ8icKr5ctZ/7Uyy0Mb2Rg/gJx+v46/T7t6b9t/SUkmG2PxzLW7vXOgqO+Biw7kyIkLqsFJBNMjEFjddl6ZbFkB1oJazJ X-Gm-Message-State: AOJu0YxkDXGGoC5bOVOVJxa2g8/aXIB6tlFa/InvMAwmj2Q3qxwOn9PR +YHh8xn8GEz88v6l7HEuA+WLY9hC8RY2/v+3MKWi84O4uZf7gl1EpF3X7ESzfvyjTfb8YGw0JIA fOdgzZNUnqPUlsVf6Is9OG0tAIac= X-Received: by 2002:a05:6122:2010:b0:4e9:7e39:cc9e with SMTP id 71dfb90a1353d-4eb3a4dc39bmr6795855e0c.10.1717676156610; Thu, 06 Jun 2024 05:15:56 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240605074936.578687-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20240605074936.578687-5-prabhakar.mahadev-lad.rj@bp.renesas.com> <20240606100810.eskr7bd3oqpphaxh@ninjato> In-Reply-To: <20240606100810.eskr7bd3oqpphaxh@ninjato> From: "Lad, Prabhakar" Date: Thu, 6 Jun 2024 13:15:30 +0100 Message-ID: Subject: Re: [RFC PATCH 4/4] mmc: renesas_sdhi: Add support for RZ/V2H(P) SoC To: Wolfram Sang , Prabhakar , Geert Uytterhoeven , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown , Magnus Damm , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Fabrizio Castro , Biju Das , Lad Prabhakar Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Wolfram, On Thu, Jun 6, 2024 at 11:08=E2=80=AFAM Wolfram Sang wrote: > > Hi Prabhakar, > > thanks for this series! > > On Wed, Jun 05, 2024 at 08:49:36AM +0100, Prabhakar wrote: > > From: Lad Prabhakar > > > > The SDHI/eMMC IPs found in the RZ/V2H(P) (a.k.a. r9a09g057) are very > > similar to those found in R-Car Gen3. However, they are not identical, > > necessitating an SoC-specific compatible string for fine-tuning driver > > support. > > > > Key features of the RZ/V2H(P) SDHI/eMMC IPs include: > > - Voltage level control via the IOVS bit. > > - PWEN pin support via SD_STATUS register. > > - Lack of HS400 support. > > - Fixed address mode operation. > > > > sd_iovs and sd_pwen quirks are introduced for SoCs supporting this bit > > to handle voltage level control and power enable via SD_STATUS register= . > > Two high-level questions: > > - can't we use .enable/.disable in regulator_ops for handling pwen? > Then we could simply use regulator_en/disable in the code and be future > proof when other SDHI instances have other kinds of regulators (unless > I am mising something) > Ok let me check on this and get back. > - what about not using regmap and use set/get_voltage and friends? My > concern is that other "new" registers might appear in the future and > it will be cumbersome to handle the scattered IO regions. > I'll have to do some reading on this. Can you please point me to any example driver which does not use regmap. > That said, having a regulator is not a quirk in my book. I'd think > 'struct renesas_sdhi' is the proper place. Or? > Ok, I will move them out of quirks. Cheers, Prabhakar