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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: marvell.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MW4PR18MB5244.namprd18.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: c63848c7-4b18-44b4-b742-08dc8647aae4 X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Jun 2024 16:42:34.7067 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: G86LyoXbBSafxe9VkI5Ly8GhICU+7jA5kXNYOC+IRflLVpwmoK+lGQtspUmL3JqBSZ45F8KXafy8Uk4Z7Sa9mA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR18MB4776 X-Proofpoint-GUID: 5jzwqnbQS126sLH8m8xOWvTqT728KiYT X-Proofpoint-ORIG-GUID: 5jzwqnbQS126sLH8m8xOWvTqT728KiYT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-06_13,2024-06-06_02,2024-05-17_01 > -----Original Message----- > From: Vamsi Krishna Attunuru > Sent: Tuesday, June 4, 2024 9:51 PM > To: 'Greg KH' > Cc: Jerin Jacob ; Srujana Challa ; > arnd@arndb.de; linux-kernel@vger.kernel.org > Subject: RE: [EXTERNAL] Re: [PATCH v7 1/1] misc: mrvl-cn10k-dpi: add Octe= on > CN10K DPI administrative driver >=20 >=20 >=20 > > -----Original Message----- > > From: Greg KH > > Sent: Tuesday, June 4, 2024 9:23 PM > > To: Vamsi Krishna Attunuru > > Cc: Jerin Jacob ; Srujana Challa > > ; arnd@arndb.de; linux-kernel@vger.kernel.org > > Subject: [EXTERNAL] Re: [PATCH v7 1/1] misc: mrvl-cn10k-dpi: add > > Octeon CN10K DPI administrative driver > > > > Prioritize security for external emails: Confirm sender and content > > safety before clicking links or opening attachments > > > > ---------------------------------------------------------------------- > > On Mon, May 20, 2024 at 04:06:30AM -0700, Vamsi Attunuru wrote: > > > +union dpi_mbox_message { > > > + u64 word[2]; > > > + struct { > > > +#if defined(__BIG_ENDIAN_BITFIELD) > > > + /* SSO PF function */ > > > + u64 sso_pf_func :16; > > > + /* Aura of the command buffer */ > > > + u64 aura :20; > > > + /* Command buffer size in 8-byte words */ > > > + u64 csize :16; > > > + /* Command code */ > > > + u64 cmd :4; > > > + /* VF ID to configure */ > > > + u64 vfid :8; > > > + /* Reserved for future use */ > > > + u64 rsvd_85_127 :40; > > > + /* Work queue completion status byte offset */ > > > + u64 wqecsoff :7; > > > + /* Work queue completion status enable */ > > > + u64 wqecs :1; > > > + /* NPA PF function */ > > > + u64 npa_pf_func :16; > > > +#else > > > + /* VF ID to configure */ > > > + u64 vfid :8; > > > + /* Command code */ > > > + u64 cmd :4; > > > + /* Command buffer size in 8-byte words */ > > > + u64 csize :16; > > > + /* Aura of the command buffer */ > > > + u64 aura :20; > > > + /* SSO PF function */ > > > + u64 sso_pf_func :16; > > > + /* NPA PF function */ > > > + u64 npa_pf_func :16; > > > + /* Work queue completion status enable */ > > > + u64 wqecs :1; > > > + /* Work queue completion status byte offset */ > > > + u64 wqecsoff :7; > > > + /* Reserved for future use */ > > > + u64 rsvd_85_127 :40; > > > +#endif > > > + }; > > > +}; > > > > The ifdef is cute, but not correct, sorry. Please use bit shifts to > > handle this properly without any #ifdef needed at all. > > > Ack, will fix it next version. Thanks for the suggestion. >=20 Hi Greg, the ARM64 cores on the Octeon CN10K hardware platform always run i= n LE mode and this CN10K DPI PF driver is only supported on Octeon CN10K pl= atforms as the DPI PF device is an onboard PCIe device. Can I remove the BE= format and only define the LE format for the dpi_mbox_message structure?, = other HW device drivers of Octeon CN10K platform also only support LE forma= t. Regards Vamsi > > > > > > > > > + > > > +static inline void dpi_reg_write(struct dpipf *dpi, u64 offset, u64 > > > +val) { > > > + writeq(val, dpi->reg_base + offset); > > > > No read needed after a write to ensure the write made it to the > > hardware properly? >=20 > Yes, as it's an onboard PCIe device, writes will happen properly. I will = modify > it as write followed by a write barrier to avoid any reordering. >=20 > Thanks > Vamsi > > > > thanks, > > > > greg k-h