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Fri, 7 Jun 2024 00:36:46 +0000 Received: from BN9PR11MB5276.namprd11.prod.outlook.com ([fe80::b576:d3bd:c8e0:4bc1]) by BN9PR11MB5276.namprd11.prod.outlook.com ([fe80::b576:d3bd:c8e0:4bc1%5]) with mapi id 15.20.7633.033; Fri, 7 Jun 2024 00:36:46 +0000 From: "Tian, Kevin" To: Jason Gunthorpe , Nicolin Chen CC: "will@kernel.org" , "robin.murphy@arm.com" , "suravee.suthikulpanit@amd.com" , "joro@8bytes.org" , "linux-kernel@vger.kernel.org" , "iommu@lists.linux.dev" , "linux-arm-kernel@lists.infradead.org" , "linux-tegra@vger.kernel.org" , "Liu, Yi L" , "eric.auger@redhat.com" , "vasant.hegde@amd.com" , "jon.grimm@amd.com" , "santosh.shukla@amd.com" , "Dhaval.Giani@amd.com" , "shameerali.kolothum.thodi@huawei.com" Subject: RE: [PATCH RFCv1 08/14] iommufd: Add IOMMU_VIOMMU_SET_DEV_ID ioctl Thread-Topic: [PATCH RFCv1 08/14] iommufd: Add IOMMU_VIOMMU_SET_DEV_ID ioctl Thread-Index: AQHajVVl26WkVBqVE0qDV+tml8yTY7Gkmr6AgAGEQoCAABbGEIAAaX4AgAPpupCAAtXxAIAAbUsAgAAHhACAAV8OUIAAC42AgASA5ICAAfF7AIAFsh+AgAAFwACAAF+ZgIAAAdLw Date: Fri, 7 Jun 2024 00:36:46 +0000 Message-ID: References: <20240606182423.GF19897@nvidia.com> <20240607002707.GJ19897@nvidia.com> In-Reply-To: <20240607002707.GJ19897@nvidia.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BN9PR11MB5276.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 83b05a62-5477-4c11-bdcc-08dc8689e97c X-MS-Exchange-CrossTenant-originalarrivaltime: 07 Jun 2024 00:36:46.5409 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: wUrOfvpqi1RAixQj30TPtZStn8jkF5evlFvRM3BF9ouS3qcrO3dJ8ampsuJ+QGviU5Lu7ChhRZ1jhNlo3cANZg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR11MB4617 X-OriginatorOrg: intel.com > From: Jason Gunthorpe > Sent: Friday, June 7, 2024 8:27 AM >=20 > On Thu, Jun 06, 2024 at 11:44:58AM -0700, Nicolin Chen wrote: > > On Thu, Jun 06, 2024 at 03:24:23PM -0300, Jason Gunthorpe wrote: > > > On Sun, Jun 02, 2024 at 08:25:34PM -0700, Nicolin Chen wrote: > > > > > > > > I understand the appeal of doing this has been to minimize qemu > > > > > changes in its ACPI parts if we tackle that instead maybe we shou= ld > > > > > just not implement viommu to multiple piommu. It is somewhat > > > > > complicated. > > > > > > > > Would you please clarify that suggestion "not implement viommu > > > > to multiple piommu"? > > > > > > > > For regular nesting (SMMU), we are still doing one vSMMU in the > > > > VMM, though VCMDQ case would be an exception.... > > > > > > This is what I mean, always do multiple vSMMU if there are multiple > > > physical pSMMUs. Don't replicate any virtual commands across pSMMUs. > > > > Thanks for clarifying. That also means you'd prefer putting the > > command dispatcher in VMM, which is what we have at this moment. >=20 > Unless someone knows a reason why we should strive hard to have only a > single vSMMU and accept some invalidation inefficiency? >=20 migration? a single vSMMU provides better compatibility between src/dest...