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Fri, 7 Jun 2024 04:40:33 +0000 From: Selvamani Rajagopal To: Andrew Lunn CC: "Parthiban.Veerasooran@microchip.com" , Piergiorgio Beruto , "davem@davemloft.net" , "edumazet@google.com" , "kuba@kernel.org" , "pabeni@redhat.com" , "horms@kernel.org" , "saeedm@nvidia.com" , "anthony.l.nguyen@intel.com" , "netdev@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "corbet@lwn.net" , "linux-doc@vger.kernel.org" , "robh+dt@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "conor+dt@kernel.org" , "devicetree@vger.kernel.org" , "Horatiu.Vultur@microchip.com" , "ruanjinjie@huawei.com" , "Steen.Hegelund@microchip.com" , "vladimir.oltean@nxp.com" , "UNGLinuxDriver@microchip.com" , "Thorsten.Kummermehr@microchip.com" , "Nicolas.Ferre@microchip.com" , "benjamin.bigler@bernformulastudent.ch" , Viliam Vozar , Arndt Schuebel Subject: RE: [PATCH net-next v4 00/12] Add support for OPEN Alliance 10BASE-T1x MACPHY Serial Interface Thread-Topic: [PATCH net-next v4 00/12] Add support for OPEN Alliance 10BASE-T1x MACPHY Serial Interface Thread-Index: AQHakZAzTzY8uLDqjU+aLRkJ24TPX7F0voeAgAA2YYCAGHiwAIAAQuMAgAFPWgCAAH78AIAA9q2AgBaZtCCAAA/6AIAABQ4AgAACngCACKHOAIABvDqAgAAGhgCAACuYgIAEK/gAgAQWz/CAACdPAIAABqdggADbbICAAQMcwA== Date: Fri, 7 Jun 2024 04:40:33 +0000 Message-ID: References: <0581b64a-dd7a-43d7-83f7-657ae93cefe5@lunn.ch> <39a62649-813a-426c-a2a6-4991e66de36e@microchip.com> <585d7709-bcee-4a0e-9879-612bf798ed45@lunn.ch> <732ce616-9ddc-4564-ab1f-ac7bbc591292@lunn.ch> <79f61e42-c32f-4314-8b77-99880c2d7eeb@lunn.ch> In-Reply-To: <79f61e42-c32f-4314-8b77-99880c2d7eeb@lunn.ch> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: BYAPR02MB5958:EE_|PH0PR02MB8860:EE_ x-ms-office365-filtering-correlation-id: a51add4b-59d6-4178-84a6-08dc86abf791 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0;ARA:13230031|7416005|1800799015|366007|376005|38070700009; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: onsemi.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BYAPR02MB5958.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: a51add4b-59d6-4178-84a6-08dc86abf791 X-MS-Exchange-CrossTenant-originalarrivaltime: 07 Jun 2024 04:40:33.0401 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 04e1674b-7af5-4d13-a082-64fc6e42384c X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: W0yBgYKzcJzdDnakXGpgWVdx8ayn2Ghb1OBqEOD8LakkKHtP/aUpfcHsvCL4AAUUbs8E2m/JkYug9jF/0bF1/OeOmSUCtKwAZGwLVw4eGXg= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR02MB8860 X-Proofpoint-ORIG-GUID: 4Nhxi6JQtE2G00GG7rRnUEzXeFwFE_sI X-Proofpoint-GUID: 4Nhxi6JQtE2G00GG7rRnUEzXeFwFE_sI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-06_20,2024-06-06_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 spamscore=0 malwarescore=0 clxscore=1015 impostorscore=0 mlxscore=0 priorityscore=1501 adultscore=0 mlxlogscore=999 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405170001 definitions=main-2406070031 > -----Original Message----- > From: Andrew Lunn > Sent: Thursday, June 6, 2024 6:12 AM > To: Selvamani Rajagopal > Cc: Parthiban.Veerasooran@microchip.com; Piergiorgio Beruto > ; davem@davemloft.net; > edumazet@google.com; kuba@kernel.org; pabeni@redhat.com; > horms@kernel.org; saeedm@nvidia.com; anthony.l.nguyen@intel.com; > netdev@vger.kernel.org; linux-kernel@vger.kernel.org; corbet@lwn.net; > linux-doc@vger.kernel.org; robh+dt@kernel.org; > krzysztof.kozlowski+dt@linaro.org; conor+dt@kernel.org; > devicetree@vger.kernel.org; Horatiu.Vultur@microchip.com; > ruanjinjie@huawei.com; Steen.Hegelund@microchip.com; > vladimir.oltean@nxp.com; UNGLinuxDriver@microchip.com; > Thorsten.Kummermehr@microchip.com; Nicolas.Ferre@microchip.com; > benjamin.bigler@bernformulastudent.ch; Viliam Vozar > ; Arndt Schuebel > > Subject: Re: [PATCH net-next v4 00/12] Add support for OPEN Alliance > 10BASE-T1x MACPHY Serial Interface >=20 > [External Email]: This email arrived from an external source - Please > exercise caution when opening any attachments or clicking on links. >=20 > > I believe my client is configured to wrap at 70th characters. > > Not sure why it is not doing it. >=20 >=20 > It could be you also send a MIME obfuscated copy which is not wrapped > correctly? >=20 > > > > 1) Can we move memory map selector definitions > > > (OA_TC6_PHY_C45_PCS_MMS2 and other 4 definitions) to the header > > > file > > > > include/linux/oa_tc6.h? > > > > Also, if possible, could we add the MMS0, MMS1?. Our driver is > > > using them. Of course, we could add it when we submit our driver. > > > > > > Interesting. So you have vendor registers outside of MMS 10-15? > > > > This is not about vendor registers. The current oa_tc6 defines > > MMS selector values for 2, 3, 4, 5, 6. I am asking, if 0, 1 can be adde= d, > > which are meant for "Standard Control and Status" and MAC > respectively, > > according to MMS assignment table 6 on OA standard. >=20 > But why would a MAC driver need access to those? Everything using > those registers should be defined in the standard. So the framework > should handle them. >=20 > > One example I can think of is, to handle PHYINT status bit > > that may be set in STATUS0 register. Another example could be, > > to give a vendor flexibility to not to use interrupt mode. >=20 > But that is part of the standard. Why would a driver need to do > anything, the framework should handle PHYINT, calling > phy_mac_interrupt(phydev). >=20 > I really think you need to post patches. We can then discuss each use > case, and i can give you concrete feedback. True. That would be better. Will work on the patches so that it is clear. >=20 > But in general, if it is part of the standard it should be in the > framework. Support for features which are not part of the standard, > and workarounds for where a device violates the standard, should be in > the MAC driver, or the PHY driver. >=20 > Andrew